公开(公告)号：US20250098272A1

公开(公告)日：2025-03-20

申请号：US18969191

申请日：2024-12-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Wen Zhang ,  Kun-Chen Ho ,  Chun-Lung Chen ,  Chung-Yi Chiu ,  Ming-Chou Lu

IPC: H01L29/49 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming an interlayer dielectric (ILD) layer on the gate structure, forming a contact hole in the ILD layer adjacent to the gate structure, performing a plasma doping process to form a doped layer in the ILD layer and a source/drain region adjacent to the gate structure, forming a conductive layer in the contact hole, planarizing the conductive layer to form a contact plug, removing the doped layer to form an air gap adjacent to the contact plug, and then forming a stop layer on the ILD layer and the contact plug.

公开(公告)号：US20220302369A1

公开(公告)日：2022-09-22

申请号：US17239667

申请日：2021-04-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Bo-Yun Huang ,  Wen-Wen Zhang ,  Kun-Chen Ho

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12

Abstract: A magnetoresistive random access memory (MRAM) structure is provided in the present invention, including multiple MRAM cells, and an atomic layer deposition dielectric layer between and at outer sides of the MRAM cells, wherein the material of top electrode layer is titanium nitride, and the nitrogen percentage is greater than titanium percentage and further greater than oxygen percentage in the titanium nitride, and the nitrogen percentage gradually increases inward from the top surface of top electrode layer to a depth and then start to gradually decrease to a first level and then remains constant, and the titanium percentage gradually decreases inward from the top surface of top electrode layer to the depth and then start to gradually increase to a second level and then remains constant.

公开(公告)号：US12206007B2

公开(公告)日：2025-01-21

申请号：US17868753

申请日：2022-07-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Wen Zhang ,  Kun-Chen Ho ,  Chun-Lung Chen ,  Chung-Yi Chiu ,  Ming-Chou Lu

IPC: H01L29/49 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming an interlayer dielectric (ILD) layer on the gate structure, forming a contact hole in the ILD layer adjacent to the gate structure, performing a plasma doping process to form a doped layer in the ILD layer and a source/drain region adjacent to the gate structure, forming a conductive layer in the contact hole, planarizing the conductive layer to form a contact plug, removing the doped layer to form an air gap adjacent to the contact plug, and then forming a stop layer on the ILD layer and the contact plug.

公开(公告)号：US20230411489A1

公开(公告)日：2023-12-21

申请号：US17868753

申请日：2022-07-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Wen Zhang ,  Kun-Chen Ho ,  Chun-Lung Chen ,  Chung-Yi Chiu ,  Ming-Chou Lu

IPC: H01L29/49 ,  H01L29/78 ,  H01L29/417 ,  H01L29/66 ,  H01L29/40

CPC classification number: H01L29/4991 ,  H01L29/7833 ,  H01L29/41775 ,  H01L29/66492 ,  H01L29/401

Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming an interlayer dielectric (ILD) layer on the gate structure, forming a contact hole in the ILD layer adjacent to the gate structure, performing a plasma doping process to form a doped layer in the ILD layer and a source/drain region adjacent to the gate structure, forming a conductive layer in the contact hole, planarizing the conductive layer to form a contact plug, removing the doped layer to form an air gap adjacent to the contact plug, and then forming a stop layer on the ILD layer and the contact plug.

公开(公告)号：US11882769B2

公开(公告)日：2024-01-23

申请号：US17239667

申请日：2021-04-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Bo-Yun Huang ,  Wen-Wen Zhang ,  Kun-Chen Ho

IPC: H01L43/02 ,  H10N50/80 ,  H10B61/00 ,  H10N50/01

CPC classification number: H10N50/80 ,  H10B61/00 ,  H10N50/01

Abstract: A magnetoresistive random access memory (MRAM) structure is provided in the present invention, including multiple MRAM cells, and an atomic layer deposition dielectric layer between and at outer sides of the MRAM cells, wherein the material of top electrode layer is titanium nitride, and the nitrogen percentage is greater than titanium percentage and further greater than oxygen percentage in the titanium nitride, and the nitrogen percentage gradually increases inward from the top surface of top electrode layer to a depth and then start to gradually decrease to a first level and then remains constant, and the titanium percentage gradually decreases inward from the top surface of top electrode layer to the depth and then start to gradually increase to a second level and then remains constant.

公开(公告)号：US20230411213A1

公开(公告)日：2023-12-21

申请号：US17868786

申请日：2022-07-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Wen Zhang ,  Ming-Chou Lu ,  Kun-Chen Ho ,  Dien-Yang Lu ,  Chun-Lung Chen ,  Chung-Yi Chiu

IPC: H01L21/768 ,  H01L23/528 ,  H01L21/311 ,  H01L29/66

CPC classification number: H01L21/76897 ,  H01L21/76832 ,  H01L21/7682 ,  H01L23/528 ,  H01L21/31116 ,  H01L29/66545

Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming a contact etch stop layer (CESL) on the gate structure, forming an interlayer dielectric (ILD) layer on the CESL, forming a contact plug in the ILD layer and adjacent to the gate structure, forming a first stop layer on the ILD layer, and removing the first stop layer and the ILD layer around the gate structure to form an air gap exposing the CESL.

公开(公告)号：US20250098273A1

公开(公告)日：2025-03-20

申请号：US18969201

申请日：2024-12-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Wen Zhang ,  Kun-Chen Ho ,  Chun-Lung Chen ,  Chung-Yi Chiu ,  Ming-Chou Lu

IPC: H01L29/49 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes a gate structure on a substrate, a source/drain region adjacent to the gate structure, an interlayer dielectric (ILD) layer around the gate structure, a contact plug in the ILD layer and adjacent to the gate structure, an air gap around the contact plug, a barrier layer on and sealing the air gap, a metal layer on the barrier layer, a stop layer adjacent to the barrier layer and on the ILD layer, and an inter-metal dielectric (IMD) layer on the ILD layer. Preferably, bottom surfaces of the barrier layer and the stop layer are coplanar and top surfaces of the IMD layer and the barrier layer are coplanar.

公开(公告)号：US20250098271A1

公开(公告)日：2025-03-20

申请号：US18969172

申请日：2024-12-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Wen Zhang ,  Kun-Chen Ho ,  Chun-Lung Chen ,  Chung-Yi Chiu ,  Ming-Chou Lu

IPC: H01L29/49 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming an interlayer dielectric (ILD) layer on the gate structure, forming a contact hole in the ILD layer adjacent to the gate structure, performing a plasma doping process to form a doped layer in the ILD layer and a source/drain region adjacent to the gate structure, forming a conductive layer in the contact hole, planarizing the conductive layer to form a contact plug, removing the doped layer to form an air gap adjacent to the contact plug, and then forming a stop layer on the ILD layer and the contact plug.