公开(公告)号：US20140295650A1

公开(公告)日：2014-10-02

申请号：US13851113

申请日：2013-03-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Jung Li ,  Chia-Jui Liang ,  Po-Chao Tsao ,  Ching-Ling Lin ,  En-Chiuan Liou

IPC: H01L21/308 ,  H01L21/311 ,  H01L21/02

CPC classification number: H01L21/308 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/76229

Abstract: A method of fabricating a patterned structure of a semiconductor device is provided. First, a substrate having a first region and a second region is provided. A target layer, a hard mask layer and a first patterned mask layer are then sequentially formed on the substrate. A first etching process is performed by using the first patterned mask layer as an etch mask so that a patterned hard mask layer is therefore formed. Spacers are respectively formed on each sidewall of the patterned hard mask layer. Then, a second patterned mask layer is formed on the substrate. A second etching process is performed to etch the patterned hard mask layer in the second region. After the exposure of the spacers, the patterned hard mask layer is used as an etch mask and an exposed target layer is removed until the exposure of the corresponding substrate.

Abstract translation: 提供一种制造半导体器件的图案化结构的方法。 首先，提供具有第一区域和第二区域的基板。 然后在基板上顺序地形成目标层，硬掩模层和第一图案化掩模层。 通过使用第一图案化掩模层作为蚀刻掩模来执行第一蚀刻工艺，从而形成图案化的硬掩模层。 间隔物分别形成在图案化的硬掩模层的每个侧壁上。 然后，在基板上形成第二图案化掩模层。 执行第二蚀刻工艺以蚀刻第二区域中的图案化硬掩模层。 在间隔物曝光之后，将图案化的硬掩模层用作蚀刻掩模，并且去除曝光的目标层，直到相应的基板的曝光。

公开(公告)号：US08951918B2

公开(公告)日：2015-02-10

申请号：US13851113

申请日：2013-03-27

Applicant: United Microelectronics Corp.

Inventor： Chia-Jung Li ,  Chia-Jui Liang ,  Po-Chao Tsao ,  Ching-Ling Lin ,  En-Chiuan Liou

IPC: H01L21/311 ,  H01L21/308

CPC classification number: H01L21/308 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/76229

Abstract: A method of fabricating a patterned structure of a semiconductor device is provided. First, a substrate having a first region and a second region is provided. A target layer, a hard mask layer and a first patterned mask layer are then sequentially formed on the substrate. A first etching process is performed by using the first patterned mask layer as an etch mask so that a patterned hard mask layer is therefore formed. Spacers are respectively formed on each sidewall of the patterned hard mask layer. Then, a second patterned mask layer is formed on the substrate. A second etching process is performed to etch the patterned hard mask layer in the second region. After the exposure of the spacers, the patterned hard mask layer is used as an etch mask and an exposed target layer is removed until the exposure of the corresponding substrate.

Abstract translation: 提供一种制造半导体器件的图案化结构的方法。 首先，提供具有第一区域和第二区域的基板。 然后在基板上顺序地形成目标层，硬掩模层和第一图案化掩模层。 通过使用第一图案化掩模层作为蚀刻掩模来执行第一蚀刻工艺，从而形成图案化的硬掩模层。 间隔物分别形成在图案化的硬掩模层的每个侧壁上。 然后，在基板上形成第二图案化掩模层。 执行第二蚀刻工艺以蚀刻第二区域中的图案化硬掩模层。 在间隔物曝光之后，将图案化的硬掩模层用作蚀刻掩模，并且去除曝光的目标层，直到相应的基板的曝光。

公开(公告)号：US20140183665A1

公开(公告)日：2014-07-03

申请号：US13728611

申请日：2012-12-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Jung Li ,  Po-Chao Tsao

IPC: H01L29/49 ,  H01L29/78

CPC classification number: H01L29/49 ,  H01L21/02057 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/82345 ,  H01L21/823842 ,  H01L21/82385 ,  H01L21/823864 ,  H01L27/0629 ,  H01L29/165 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7834 ,  H01L29/7848

Abstract: Provided is a semiconductor structure including a gate structure, a first spacer, and a second spacer. The gate structure is formed on a substrate and includes a gate material layer, a first hard mask layer disposed on the gate material layer, and a second hard mask layer disposed on the first hard mask layer. The first spacer is disposed on sidewalls of the gate structure. The second spacer is disposed adjacent to the first spacer. The etch rate of the first hard mask layer, the etch rate of the first spacer, and the etch rate of the second spacer are substantially the same and significantly smaller than the etch rate of the second hard mask layer in a rinsing solution.

Abstract translation: 提供了包括栅极结构，第一间隔物和第二间隔物的半导体结构。 栅极结构形成在基板上，包括栅极材料层，设置在栅极材料层上的第一硬掩模层和设置在第一硬掩模层上的第二硬掩模层。 第一间隔件设置在栅极结构的侧壁上。 第二间隔件邻近第一间隔件设置。 第一硬掩模层的蚀刻速率，第一间隔物的蚀刻速率和第二间隔物的蚀刻速率与漂洗溶液中的第二硬掩模层的蚀刻速率基本相同并显着小于第二硬掩模层的蚀刻速率。

公开(公告)号：US08883621B2

公开(公告)日：2014-11-11

申请号：US13728611

申请日：2012-12-27

Applicant: United Microelectronics Corp.

Inventor： Chia-Jung Li ,  Po-Chao Tsao

IPC: H01L21/8238 ,  H01L21/336 ,  H01L29/49 ,  H01L29/78 ,  H01L27/06 ,  H01L21/8234

CPC classification number: H01L29/49 ,  H01L21/02057 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/82345 ,  H01L21/823842 ,  H01L21/82385 ,  H01L21/823864 ,  H01L27/0629 ,  H01L29/165 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7834 ,  H01L29/7848

Abstract: Provided is a semiconductor structure including a gate structure, a first spacer, and a second spacer. The gate structure is formed on a substrate and includes a gate material layer, a first hard mask layer disposed on the gate material layer, and a second hard mask layer disposed on the first hard mask layer. The first spacer is disposed on sidewalls of the gate structure. The second spacer is disposed adjacent to the first spacer. The etch rate of the first hard mask layer, the etch rate of the first spacer, and the etch rate of the second spacer are substantially the same and significantly smaller than the etch rate of the second hard mask layer in a rinsing solution.

Abstract translation: 提供了包括栅极结构，第一间隔物和第二间隔物的半导体结构。 栅极结构形成在基板上，包括栅极材料层，设置在栅极材料层上的第一硬掩模层和设置在第一硬掩模层上的第二硬掩模层。 第一间隔件设置在栅极结构的侧壁上。 第二间隔件邻近第一间隔件设置。 第一硬掩模层的蚀刻速率，第一间隔物的蚀刻速率和第二间隔物的蚀刻速率与漂洗溶液中的第二硬掩模层的蚀刻速率基本相同并显着小于第二硬掩模层的蚀刻速率。