公开(公告)号：US20150194348A1

公开(公告)日：2015-07-09

申请号：US14659576

申请日：2015-03-16

Applicant: United Microelectronics Corp.

Inventor： Chia-Jui Liang ,  Po-Chao Tsao

IPC: H01L21/8234 ,  H01L29/423 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L21/823468 ,  H01L21/02068 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823462 ,  H01L27/088 ,  H01L29/165 ,  H01L29/4232 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66636 ,  H01L29/7848

Abstract: A semiconductor structure includes a first gate and a second gate, a first spacer and a second spacer, two first epitaxial structures and two second epitaxial structures. The first gate and the second gate are located on a substrate. The first spacer and the second spacer are respectively located on the substrate beside the first gate and the second gate. The first epitaxial structures and the second epitaxial structures are respectively located in the substrate beside the first spacer and the second spacer, wherein the first spacer and the second spacer have different thicknesses, and the spacing between the first epitaxial structures is different from the spacing between the second epitaxial structures. Moreover, the present invention also provides a semiconductor process forming said semiconductor structure.

Abstract translation: 半导体结构包括第一栅极和第二栅极，第一间隔物和第二间隔物，两个第一外延结构和两个第二外延结构。 第一栅极和第二栅极位于基板上。 第一间隔物和第二间隔物分别位于第一栅极和第二栅极旁边的衬底上。 第一外延结构和第二外延结构分别位于第一间隔物和第二间隔物旁边的衬底中，其中第一间隔物和第二间隔物具有不同的厚度，并且第一外延结构之间的间隔不同于 第二外延结构。 此外，本发明还提供了形成所述半导体结构的半导体工艺。

公开(公告)号：US08912074B2

公开(公告)日：2014-12-16

申请号：US14329982

申请日：2014-07-13

Applicant: United Microelectronics Corp.

Inventor： En-Chiuan Liou ,  Po-Chao Tsao ,  Chia-Jui Liang ,  Jia-Rong Wu

IPC: H01L21/76 ,  H01L21/762

CPC classification number: H01L29/0653 ,  H01L21/76224 ,  H01L21/76235 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0649

Abstract: A method of forming shallow trench isolation structures including the steps of forming a trench in a substrate, filling a first insulating layer in the lower portion of the trench and defining a recess at the upper portion of the trench, forming a buffer layer on the sidewall of the recess, filling a second insulating layer in the recess, and performing a steam annealing process to transform the substrate surrounding the first insulating layer into an oxide layer.

Abstract translation: 一种形成浅沟槽隔离结构的方法，包括以下步骤：在衬底中形成沟槽，填充沟槽下部的第一绝缘层并在沟槽的上部限定凹陷，在侧壁上形成缓冲层 在凹部中填充第二绝缘层，并执行蒸汽退火处理，以将围绕第一绝缘层的基板转变为氧化物层。

公开(公告)号：US20140322891A1

公开(公告)日：2014-10-30

申请号：US14329982

申请日：2014-07-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Po-Chao Tsao ,  Chia-Jui Liang ,  Jia-Rong Wu

IPC: H01L21/762

CPC classification number: H01L29/0653 ,  H01L21/76224 ,  H01L21/76235 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0649

Abstract: A method of forming shallow trench isolation structures including the steps of forming a trench in a substrate, filling a first insulating layer in the lower portion of the trench and defining a recess at the upper portion of the trench, forming a buffer layer on the sidewall of the recess, filling a second insulating layer in the recess, and performing a steam annealing process to transform the substrate surrounding the first insulating layer into an oxide layer.

Abstract translation: 一种形成浅沟槽隔离结构的方法，包括以下步骤：在衬底中形成沟槽，填充沟槽下部的第一绝缘层并在沟槽的上部限定凹陷，在侧壁上形成缓冲层 在凹部中填充第二绝缘层，并执行蒸汽退火处理，以将围绕第一绝缘层的基板转变为氧化物层。

公开(公告)号：US08823132B2

公开(公告)日：2014-09-02

申请号：US13736082

申请日：2013-01-08

Applicant: United Microelectronics Corp.

Inventor： En-Chiuan Liou ,  Po-Chao Tsao ,  Chia-Jui Liang ,  Jia-Rong Wu

IPC: H01L29/00

CPC classification number: H01L29/0653 ,  H01L21/76224 ,  H01L21/76235 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0649

Abstract: A shallow trench isolation (STI) and method of forming the same is provided. The STI structure comprises an upper insulating portion and a lower insulating portion, wherein the lower insulating portion includes a first insulator and an insulating layer surrounding the first insulator, the upper insulating portion includes a second insulator and a buffer layer surrounding the second insulator. A part of the buffer layer interfaces between the first insulator and the second insulator, and the outer sidewall of the buffer layer and the sidewall of the first insulator are leveled.

Abstract translation: 提供浅沟槽隔离（STI）及其形成方法。 STI结构包括上绝缘部分和下绝缘部分，其中下绝缘部分包括第一绝缘体和围绕第一绝缘体的绝缘层，上绝缘部分包括第二绝缘体和围绕第二绝缘体的缓冲层。 缓冲层的一部分在第一绝缘体和第二绝缘体之间接合，缓冲层的外侧壁和第一绝缘体的侧壁平整。

公开(公告)号：US20140183642A1

公开(公告)日：2014-07-03

申请号：US13728948

申请日：2012-12-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Jui Liang ,  Po-Chao Tsao

IPC: H01L29/66 ,  H01L27/088

CPC classification number: H01L21/823468 ,  H01L21/02068 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823462 ,  H01L27/088 ,  H01L29/165 ,  H01L29/4232 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66636 ,  H01L29/7848

Abstract: A semiconductor structure includes a first gate and a second gate, a first spacer and a second spacer, two first epitaxial structures and two second epitaxial structures. The first gate and the second gate are located on a substrate. The first spacer and the second spacer are respectively located on the substrate beside the first gate and the second gate. The first epitaxial structures and the second epitaxial structures are respectively located in the substrate beside the first spacer and the second spacer, wherein the first spacer and the second spacer have different thicknesses, and the spacing between the first epitaxial structures is different from the spacing between the second epitaxial structures. Moreover, the present invention also provides a semiconductor process forming said semiconductor structure.

Abstract translation: 半导体结构包括第一栅极和第二栅极，第一间隔物和第二间隔物，两个第一外延结构和两个第二外延结构。 第一栅极和第二栅极位于基板上。 第一间隔物和第二间隔物分别位于第一栅极和第二栅极旁边的衬底上。 第一外延结构和第二外延结构分别位于第一间隔物和第二间隔物旁边的衬底中，其中第一间隔物和第二间隔物具有不同的厚度，并且第一外延结构之间的间隔不同于 第二外延结构。 此外，本发明还提供了形成所述半导体结构的半导体工艺。

公开(公告)号：US09337260B2

公开(公告)日：2016-05-10

申请号：US14549559

申请日：2014-11-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Po-Chao Tsao ,  Chia-Jui Liang ,  Jia-Rong Wu

IPC: H01L29/06 ,  H01L27/088 ,  H01L21/762 ,  H01L21/8234

CPC classification number: H01L29/0653 ,  H01L21/76224 ,  H01L21/76235 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0649

Abstract: The semiconductor structure includes a plurality of first insulators in a substrate, a common insulating layer surrounding the sidewall and the bottom of said first insulators in said substrate, and suspended portions of said substrate on said common insulating layer.

Abstract translation: 半导体结构包括在基板中的多个第一绝缘体，围绕所述基板中的所述第一绝缘体的侧壁和底部的公共绝缘层，以及在所述公共绝缘层上的所述基板的悬置部分。

公开(公告)号：US09330980B2

公开(公告)日：2016-05-03

申请号：US14659576

申请日：2015-03-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Jui Liang ,  Po-Chao Tsao

IPC: H01L21/336 ,  H01L27/092 ,  H01L29/76 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/088 ,  H01L29/78 ,  H01L29/165 ,  H01L21/02 ,  H01L29/423

CPC classification number: H01L21/823468 ,  H01L21/02068 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823462 ,  H01L27/088 ,  H01L29/165 ,  H01L29/4232 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66636 ,  H01L29/7848

Abstract: A semiconductor structure includes a first gate and a second gate, a first spacer and a second spacer, two first epitaxial structures and two second epitaxial structures. The first gate and the second gate are located on a substrate. The first spacer and the second spacer are respectively located on the substrate beside the first gate and the second gate. The first epitaxial structures and the second epitaxial structures are respectively located in the substrate beside the first spacer and the second spacer, wherein the first spacer and the second spacer have different thicknesses, and the spacing between the first epitaxial structures is different from the spacing between the second epitaxial structures. Moreover, the present invention also provides a semiconductor process forming said semiconductor structure.

Abstract translation: 半导体结构包括第一栅极和第二栅极，第一间隔物和第二间隔物，两个第一外延结构和两个第二外延结构。 第一栅极和第二栅极位于基板上。 第一间隔物和第二间隔物分别位于第一栅极和第二栅极旁边的衬底上。 第一外延结构和第二外延结构分别位于第一间隔物和第二间隔物旁边的衬底中，其中第一间隔物和第二间隔物具有不同的厚度，并且第一外延结构之间的间隔不同于 第二外延结构。 此外，本发明还提供了形成所述半导体结构的半导体工艺。

公开(公告)号：US09190291B2

公开(公告)日：2015-11-17

申请号：US13934236

申请日：2013-07-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Jui Liang ,  Po-Chao Tsao ,  Jun-Jie Wang ,  Chih-Sen Huang

IPC: H01L21/311

CPC classification number: H01L21/31144 ,  H01L21/3086 ,  H01L29/66795

Abstract: A fin-shaped structure forming process includes the following step. A first mandrel and a second mandrel are formed on a substrate. A first spacer material is formed to entirely cover the first mandrel, the second mandrel and the substrate. The exposed first spacer material is etched to form a first spacer on the substrate beside the first mandrel. A second spacer material is formed to entirely cover the first mandrel, the second mandrel and the substrate. The second spacer material and the first spacer material are etched to form a second spacer on the substrate beside the second mandrel and a third spacer including the first spacer on the substrate beside the first mandrel. The layout of the second spacer and the third spacer is transferred to the substrate, so a second fin-shaped structure and a first fin-shaped structure having different widths are formed respectively.

Abstract translation: 鳍状结构形成工序包括以下工序。 第一心轴和第二心轴形成在基底上。 形成第一间隔材料以完全覆盖第一心轴，第二心轴和基底。 蚀刻暴露的第一间隔物材料以在第一心轴旁边的基底上形成第一间隔物。 形成第二间隔材料以完全覆盖第一心轴，第二心轴和基底。 蚀刻第二间隔物材料和第一间隔物材料以在第二心轴旁边的基底上形成第二间隔物，以及在第一心轴旁边的包括在基底上的第一间隔物的第三间隔物。 第二间隔物和第三间隔物的布局被转移到基底，因此分别形成具有不同宽度的第二鳍状结构和第一鳍状结构。

公开(公告)号：US09159798B2

公开(公告)日：2015-10-13

申请号：US13886382

申请日：2013-05-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jun-Jie Wang ,  Po-Chao Tsao ,  Chia-Jui Liang ,  Shih-Fang Tzou ,  Chien-Ting Lin ,  Cheng-Guo Chen ,  Ssu-I Fu ,  Yu-Hsiang Hung ,  Chung-Fu Chang

IPC: H01L21/8238 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/42364 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/7851

Abstract: A replacement gate process is disclosed. A substrate and a dummy gate structure formed on the substrate is provided, wherein the dummy gate structure comprises a dummy layer on the substrate, a hard mask layer on the dummy layer, spacers at two sides of the dummy layer and the hard mask layer, and a contact etch stop layer (CESL) covering the substrate, the spacers and the hard mask layer. The spacers and the CESL are made of the same material. Then, a top portion of the CESL is removed to expose the hard mask layer. Next, the hard mask layer is removed. Afterward, the dummy layer is removed to form a trench.

Abstract translation: 公开了替代浇口工艺。 提供了一种在基板上形成的基板和虚拟栅极结构，其中，虚设栅极结构包括基板上的虚设层，虚设层上的硬掩模层，虚设层两侧的间隔物和硬掩模层， 以及覆盖衬底，间隔物和硬掩模层的接触蚀刻停止层（CESL）。 垫片和CESL由相同的材料制成。 然后，去除CESL的顶部以露出硬掩模层。 接下来，去除硬掩模层。 之后，去除虚拟层以形成沟槽。

公开(公告)号：US09117925B2

公开(公告)日：2015-08-25

申请号：US13756464

申请日：2013-01-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Jui Liang ,  Po-Chao Tsao

IPC: H01L21/8238 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L29/165

CPC classification number: H01L21/823418 ,  H01L21/823412 ,  H01L21/823468 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: An epitaxial process includes the following steps. A substrate including a first area and a second area is provided. A first gate and a second gate are formed respectively on the substrate of the first area and the second area. A first spacer and a second spacer are respectively formed on the substrate beside the first gate and the second gate at the same time. A first epitaxial structure is formed beside the first spacer and then a second epitaxial structure is formed beside the second spacer by the first spacer and the second spacer respectively.

Abstract translation: 外延工艺包括以下步骤。 提供了包括第一区域和第二区域的基板。 第一栅极和第二栅极分别形成在第一区域和第二区域的基板上。 第一间隔物和第二间隔物同时分别形成在第一栅极和第二栅极旁边的基板上。 在第一间隔物旁边形成第一外延结构，然后通过第一间隔物和第二间隔物分别在第二间隔物旁边形成第二外延结构。