公开(公告)号：US20250046372A1

公开(公告)日：2025-02-06

申请号：US18367488

申请日：2023-09-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shu-Hung Yu ,  Chuan-Fu Wang ,  Chung-Chin Shih

IPC: G11C13/00

Abstract: A memory includes a first switch transistor, a second switch transistor, a third switch transistor, a fourth switch transistor, a first resistive memory element and a second resistive memory element. Each of the first switch transistor, the second switch transistor, the third switch transistor and the fourth switch transistor includes a drain terminal, a source terminal and a gate terminal. The drain terminal of the third switch transistor is coupled to the source terminal of the first switch transistor. The drain terminal of the fourth switch transistor is coupled to the source terminal of the second switch transistor. The first resistive memory element is coupled to the source terminal of the fourth switch transistor and the source terminal of the first switch transistor. The second resistive memory element is coupled to the source terminal of the third switch transistor and the source terminal of the second switch transistor.

公开(公告)号：US12193345B2

公开(公告)日：2025-01-07

申请号：US18503140

申请日：2023-11-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Jen Wang ,  Chun-Hung Cheng ,  Chuan-Fu Wang

IPC: H10N70/20 ,  H10B63/00 ,  H10N70/00

Abstract: A resistive random access memory (RRAM) structure includes a RRAM cell, spacers and a dielectric layer. The RRAM cell is disposed on a substrate. The spacers are disposed beside the RRAM cell, wherein widths of top surfaces of the spacers are larger than or equal to widths of bottom surfaces of the spacers. The dielectric layer blanketly covers the substrate and sandwiches the RRAM cell, wherein the spacers are located in the dielectric layer. A method for forming the resistive random access memory (RRAM) structure is also provided.

公开(公告)号：US11882773B2

公开(公告)日：2024-01-23

申请号：US17396493

申请日：2021-08-06

Applicant: United Microelectronics Corp.

Inventor： Kai Jiun Chang ,  Chun-Hung Cheng ,  Chuan-Fu Wang

IPC: H10N70/00 ,  H10N70/20

CPC classification number: H10N70/828 ,  H10N70/023 ,  H10N70/063 ,  H10N70/24 ,  H10N70/841 ,  H10N70/8833 ,  H10N70/8836

Abstract: Provided are a resistive random access memory (RRAM) and a manufacturing method thereof. The resistive random access memory includes multiple unit structures disposed on a substrate. Each of the unit structures includes a first electrode, a first metal oxide layer, and a spacer. The first electrode is disposed on the substrate. The first metal oxide layer is disposed on the first electrode. The spacer is disposed on sidewalls of the first electrode and the first metal oxide layer. In addition, the resistive random access memory includes a second metal oxide layer and a second electrode. The second metal oxide layer is disposed on the unit structures and is connected to the unit structures. The second electrode is disposed on the second metal oxide layer.

公开(公告)号：US11770987B2

公开(公告)日：2023-09-26

申请号：US17489829

申请日：2021-09-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shu-Hung Yu ,  Chun-Hung Cheng ,  Chuan-Fu Wang

IPC: G06F12/02 ,  H10N70/00 ,  H10B63/00

CPC classification number: H10N70/841 ,  H10B63/80 ,  H10N70/026 ,  H10N70/063 ,  H10N70/066 ,  H10N70/8833

Abstract: A ReRAM device includes a dielectric layer, a bottom electrode, a data storage layer, a metal covering layer, and a top electrode. The dielectric layer has a recess. At least a portion of the bottom electrode is exposed through the recess. The data storage layer is disposed on a sidewall and a bottom surface of the recess, electrically contacts with the bottom electrode, and has a top portion lower than an opening of the recess. The metal covering layer blanket covers the data storage layer, has an extension portion covering the top portion, and connects to the sidewall of the recess. The top electrode is disposed in the recess, and is electrically contact with the metal covering layer.

公开(公告)号：US20220271223A1

公开(公告)日：2022-08-25

申请号：US17741471

申请日：2022-05-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shu-Hung Yu ,  Chun-Hung Cheng ,  Chuan-Fu Wang

IPC: H01L45/00

Abstract: A resistive random-access memory (RRAM) device includes a bottom electrode, a high work function layer, a resistive material layer, a top electrode and high work function spacers. The bottom electrode, the high work function layer, the resistive material layer and the top electrode are sequentially stacked on a substrate, wherein the resistive material layer includes a bottom part and a top part. The high work function spacers cover sidewalls of the bottom part, thereby constituting a RRAM cell. The present invention also provides a method of forming a RRAM device.

公开(公告)号：US20220223612A1

公开(公告)日：2022-07-14

申请号：US17201986

申请日：2021-03-15

Applicant: United Microelectronics Corp.

Inventor： Chia-Hung Chen ,  Yu-Huang Yeh ,  Chuan-Fu Wang

IPC: H01L27/11568 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11565

Abstract: A memory structure including a substrate, a first dielectric layer, a second dielectric layer, a charge storage layer, an oxide layer, and a conductive layer is provided. The first dielectric layer is disposed on the substrate. The second dielectric layer is disposed on the first dielectric layer. The charge storage layer is disposed between the first dielectric layer and the second dielectric layer. The oxide layer is located at two ends of the charge storage layer and is disposed between the first dielectric layer and the second dielectric layer. The conductive layer is disposed on the second dielectric layer.

公开(公告)号：US20240431219A1

公开(公告)日：2024-12-26

申请号：US18224054

申请日：2023-07-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Jen Wang ,  Yu-Huan Yeh ,  Chuan-Fu Wang

IPC: H10N70/00 ,  H10B63/00 ,  H10N70/20

Abstract: An RRAM includes a bottom electrode, a resistive switching layer, a top electrode and a cap layer stacked from bottom to top. The cap layer includes a top surface. A first spacer contacts a first sidewall of the bottom electrode, and a second sidewall of the resistive switching layer. A second spacer contacts the first spacer and contacts a third spacer of the top electrode. A thickness of the first spacer is greater of a thickness of the second spacer. The first spacer and the second spacer do not cover the topmost surface of the cap layer.

公开(公告)号：US12127488B2

公开(公告)日：2024-10-22

申请号：US17876560

申请日：2022-07-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Jen Wang ,  Chun-Hung Cheng ,  Chuan-Fu Wang

IPC: G11C11/00 ,  H10B63/00 ,  H10N70/00

CPC classification number: H10N70/8833 ,  H10B63/80 ,  H10N70/021 ,  H10N70/063 ,  H10N70/066 ,  H10N70/841

Abstract: A resistive random access memory structure includes a first inter-layer dielectric layer; a bottom electrode disposed in the first inter-layer dielectric layer; a capping layer disposed on the bottom electrode and on the first inter-layer dielectric layer; and a through hole disposed in the capping layer. The through hole partially exposes a top surface of the bottom electrode. A variable resistance layer is disposed within the through hole. A top electrode is disposed within the through hole and on the variable resistance layer. A second inter-layer dielectric layer covers the top electrode and the capping layer.

公开(公告)号：US20240260490A1

公开(公告)日：2024-08-01

申请号：US18112483

申请日：2023-02-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Jen Wang ,  Yu-Huan Yeh ,  Chuan-Fu Wang

IPC: H10N70/00 ,  H10N70/20

CPC classification number: H10N70/8418 ,  H10N70/011 ,  H10N70/24 ,  H10N70/8833

Abstract: A resistive memory device includes a substrate; a dielectric layer disposed on the substrate; a conductive via disposed in the dielectric layer; and a memory stack structure disposed on the conductive via and the dielectric layer. The memory stack structure includes a bottom electrode layer, a resistive switching layer on the bottom electrode layer, and a top electrode layer on the resistive switching layer. The top electrode layer includes at least two physically separated sub-electrode portions.

公开(公告)号：US12041863B2

公开(公告)日：2024-07-16

申请号：US17159160

申请日：2021-01-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Jen Wang ,  Chun-Hung Cheng ,  Chuan-Fu Wang

IPC: H01L45/00 ,  H10B63/00 ,  H10N70/00

CPC classification number: H10N70/8833 ,  H10B63/00 ,  H10N70/023 ,  H10N70/063 ,  H10N70/841

Abstract: A resistive random access memory (RRAM) structure includes a RRAM cell, spacers and a dielectric layer. The RRAM cell is disposed on a substrate. The spacers are disposed beside the RRAM cell, wherein widths of top surfaces of the spacers are larger than or equal to widths of bottom surfaces of the spacers. The dielectric layer blanketly covers the substrate and sandwiches the RRAM cell, wherein the spacers are located in the dielectric layer. A method for forming said resistive random access memory (RRAM) structure is also provided.