中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

14 records (took 0.012 seconds)

    Layout pattern of static random access memory and the manufacturing method thereof
    1.
    发明申请
    Layout pattern of static random access memory and the manufacturing method thereof 有权

    公开(公告)号：US20220216220A1

    公开(公告)日：2022-07-07

    申请号：US17163571

    申请日：2021-02-01

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Wei-Chi Lee ,  Shu-Wei Yeh ,  Chang-Hung Chen

    IPC: H01L27/11 ,  H01L27/092 ,  H01L21/8238

    Abstract: A layout pattern of static random access memory at least includes a substrate, a plurality of fin structures on the substrate, a plurality of gate structures on the substrate and spanning the fin structures to form a plurality of transistors distributed on the substrate, the plurality of transistors include, a first pull-up transistor PU1, a first pull-down transistor PD1, a second pull-up transistor PU2, a second pull-down transistor PD2, a first pass gate transistor PG1, a second pass gate transistor PG2, a first read transistor RPD and a second read transistor RPG, and an additional fin structure, the additional fin structure is located between the fin structure of the first pass gate transistor PG1 and the fin structure of the second read transistor RPG.

    Layout pattern of static random access memory and the manufacturing method thereof
    3.
    发明授权
    Layout pattern of static random access memory and the manufacturing method thereof 有权

    公开(公告)号：US11502088B2

    公开(公告)日：2022-11-15

    申请号：US17163571

    申请日：2021-02-01

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Wei-Chi Lee ,  Shu-Wei Yeh ,  Chang-Hung Chen

    IPC: H01L27/11 ,  H01L21/8238 ,  H01L27/092

    Abstract: A layout pattern of static random access memory at least includes a substrate, a plurality of fin structures on the substrate, a plurality of gate structures on the substrate and spanning the fin structures to form a plurality of transistors distributed on the substrate, the plurality of transistors include, a first pull-up transistor PU1, a first pull-down transistor PD1, a second pull-up transistor PU2, a second pull-down transistor PD2, a first pass gate transistor PG1, a second pass gate transistor PG2, a first read transistor RPD and a second read transistor RPG, and an additional fin structure, the additional fin structure is located between the fin structure of the first pass gate transistor PG1 and the fin structure of the second read transistor RPG.

    Layout pattern for SRAM and manufacturing methods thereof
    6.
    发明授权
    Layout pattern for SRAM and manufacturing methods thereof 有权

    公开(公告)号：US10396064B2

    公开(公告)日：2019-08-27

    申请号：US16171339

    申请日：2018-10-25

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Jun-Jie Wang ,  Yu-Lin Wang ,  Tzu-Feng Chang ,  Wei-Chi Lee

    IPC: H01L27/02 ,  G03F1/36 ,  G06F17/50 ,  G11C11/419 ,  G11C11/412 ,  H01L27/11

    Abstract: The present invention provides a layout pattern of a static random access memory (SRAM). The layout pattern includes a first inverter and a second inverter constituting a latch circuit, wherein the latch circuit includes four transistors, a first access transistor (PG1) and a second access transistor (PG2) being electrically connected to the latch circuit, wherein the first access transistor is electrically connected to a first word line and a first bit line, and the second access transistor is electrically connected to a second word line and a second bit line, the first access transistor has a first gate length, the first access transistor has a second gate length, and the first gate length is different from the second gate length, and two read transistors series connected to each other, wherein one of the two read transistors is connected to the latch circuit.

    Mask set and method for fabricating semiconductor device by using the same
    8.
    发明授权
    Mask set and method for fabricating semiconductor device by using the same 有权
    掩模套和使用该半导体器件的方法

    公开(公告)号：US09455202B2

    公开(公告)日：2016-09-27

    申请号：US14289657

    申请日：2014-05-29

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Wei-Chi Lee ,  Yu-Lin Wang ,  Chung-Yuan Lee

    IPC: H01L21/8238 ,  G03F1/00

    CPC classification number: H01L21/823842 ,  G03F1/00

    Abstract: A mask set includes a first mask and a second mask. The first mask includes geometric patterns. The second mask includes at least a strip-shaped pattern with a first edge and a second edge opposite to the first edge. The strip-shaped pattern has a centerline along a long axis of the strip-shaped pattern. The first edge includes inwardly displaced segments shifting towards the centerline and each of the inwardly displaced segments overlaps each of the geometric patterns.

    Abstract translation: 掩模组包括第一掩模和第二掩模。 第一个面具包括几何图案。 第二掩模包括至少带状的图案，其具有第一边缘和与第一边缘相对的第二边缘。 带状图案具有沿着带状图案的长轴的中心线。 第一边缘包括朝向中心线移动的向内移位的段，并且每个向内移位的段与每个几何图案重叠。

    SEMICONDUCTOR CHIP AND METHOD OF ESTIMATING CAPABILITY OF SEMICONDUCTOR MANUFACTURING SYSTEM
    9.
    发明申请
    SEMICONDUCTOR CHIP AND METHOD OF ESTIMATING CAPABILITY OF SEMICONDUCTOR MANUFACTURING SYSTEM 审中-公开
    半导体制造系统的半导体芯片和估算能力的方法

    公开(公告)号：US20160099184A1

    公开(公告)日：2016-04-07

    申请号：US14509032

    申请日：2014-10-07

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Wei-Chi Lee ,  Yu-Lin Wang ,  Chun-Chieh Chang ,  Tzu-Feng Chang ,  Po-Peng Lin

    IPC: H01L21/66 ,  H01L21/8234 ,  H01L29/10 ,  H01L27/11

    CPC classification number: H01L22/14 ,  H01L21/823412 ,  H01L21/823431 ,  H01L27/1104

    Abstract: A method of estimating the capability of a semiconductor manufacturing system is provided. Plural first transistors are formed and a first VtMM value and a first scale value are obtained. Plural second transistors are formed and a second VtMM value and a second scale value are obtained. Plural third transistors are formed and a third VtMM value and a third scale value are obtained. A first channel length of the first transistor is smaller than a second channel length of the second transistor and is equal to a third channel length of the third transistor. A VtMM v.s. scale figure is established. A line is formed by linking the first dot and the third dot and a vertical Gap between the line and the second dot is measured. The capability of the semiconductor system is determined based on the vertical Gap. The invention further provides a chip.

    Abstract translation: 提供了一种估计半导体制造系统的能力的方法。 形成多个第一晶体管，并获得第一VtMM值和第一刻度值。 形成多个第二晶体管，并获得第二VtMM值和第二刻度值。 形成多个第三晶体管，并获得第三VtMM值和第三比例值。 第一晶体管的第一沟道长度小于第二晶体管的第二沟道长度，并且等于第三晶体管的第三沟道长度。 VtMM v.s. 规模建立。 通过连接第一点和第三点形成线，并且测量线与第二点之间的垂直间隙。 基于垂直间隙确定半导体系统的能力。 本发明还提供一种芯片。

Patent Agency Ranking