公开(公告)号：US20240112914A1

公开(公告)日：2024-04-04

申请号：US18121609

申请日：2023-03-15

Applicant: University of Electronic Science and Technology of China

Inventor： Bo ZHANG ,  Teng LIU ,  Wentong ZHANG ,  Nailong HE ,  Sen ZHANG ,  Ming QIAO ,  Zhaoji LI

IPC: H01L21/033 ,  H01L21/02 ,  H01L21/027 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/3213

CPC classification number: H01L21/0337 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/0273 ,  H01L21/0332 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/32055 ,  H01L21/32137 ,  H01L21/32139

Abstract: A new variable selective etching technology for thick SOI devices. An SOI material is etched by the following steps: (1) providing an SOI wafer; (2) depositing a composite hard mask with a variable selection ratio to replace a traditional hard mask with an invariable selection ratio; (3) applying a photoresist; (4) mask making, namely defining a to-be-etched region by using a photoetching plate; (5) etching the photoresist in the defined region; (6) etching the composite hard mask; (7) removing the photoresist; (8) etching top silicon by using a second etching method at a first selection ratio; and (9) etching a buried oxide layer by using a third etching method at a second selection ratio. The new variable selective etching technology avoids the damage to a side wall of a deep trench when the buried oxide layer is etched, and does not need to use an excessive thick hard mask.

公开(公告)号：US20240055489A1

公开(公告)日：2024-02-15

申请号：US17994027

申请日：2022-11-25

Applicant: University of Electronic Science and Technology of China

Inventor： Bo ZHANG ,  Lingying WU ,  Yuting LIU ,  Wentong ZHANG ,  Zhaoji LI

IPC: H01L29/40 ,  H01L29/423

CPC classification number: H01L29/407 ,  H01L29/404 ,  H01L29/4238

Abstract: A homogenization field device with low specific on-resistance based on multidimensional coupled voltage dividing mechanism includes a first conductive type semiconductor substrate, a first conductive type well region, a first conductive type semiconductor contact region, a second conductive type drift region, a second conductive type well region, a second conductive type semiconductor contact region, a first dielectric oxide layer, a second dielectric oxide layer, a third dielectric oxide layer, a fourth dielectric oxide layer, a polycrystalline silicon electrode of a floating field plate, a polycrystalline silicon electrode of a control gate, a first layer of metal strips and a second layer of metal strips. The first dielectric oxide layer and the polycrystalline silicon electrode of the floating field plate form a vertical floating field plate, and the first layer of metal strips, the second layer of metal strips and the fourth dielectric oxide layer form a surface fixed dielectric capacitor.

公开(公告)号：US20170084728A1

公开(公告)日：2017-03-23

申请号：US15372352

申请日：2016-12-07

Applicant: UNIVERSITY OF ELECTRONIC SCIENCE AND TECHNOLOGY OF CHINA ,  INSTITUTE OF ELECTRONIC AND INFORMATION ENGINEERING IN DONGGUAN, UESTC

Inventor： Jinping ZHANG ,  Zehong LI ,  Jingxiu LIU ,  Min REN ,  Bo ZHANG ,  Zhaoji LI

IPC: H01L29/74 ,  H01L29/10 ,  H01L21/02 ,  H01L29/66 ,  H01L21/3065 ,  H01L21/265 ,  H01L29/747 ,  H01L29/40

CPC classification number: H01L29/7424 ,  H01L21/02233 ,  H01L21/26586 ,  H01L21/3065 ,  H01L29/0623 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/408 ,  H01L29/66325 ,  H01L29/66386 ,  H01L29/7394 ,  H01L29/747 ,  H01L29/78

Abstract: A bidirectional Metal-Oxide-Semiconductor (MOS) device, including a P-type substrate, and an active region. The active region includes a drift region, a first MOS structure and a second MOS structure; the first MOS structure includes a first P-type body region, a first P+ contact region, a first N+ source region, a first metal electrode, and a first gate structure; the second MOS structure includes a second P-type body region, a second P+ contact region, a second N+ source region, a second metal electrode, and a second gate structure; and the drift region includes a dielectric slot, a first N-type layer, a second N-type layer, and an N-type region. The active region is disposed on the upper surface of the P-type substrate. The first MOS structure and the second MOS structure are symmetrically disposed on two ends of the upper layer of the drift region.

公开(公告)号：US20230053369A1

公开(公告)日：2023-02-23

申请号：US17744779

申请日：2022-05-16

Applicant: University of Electronic Science and Technology of China

Inventor： Wentong ZHANG ,  Ning TANG ,  Ke ZHANG ,  Nailong HE ,  Ming QIAO ,  Zhaoji LI ,  Bo ZHANG

IPC: H01L29/06 ,  H01L29/40 ,  H01L29/739 ,  H01L29/66 ,  H01L29/78

Abstract: An SOI lateral homogenization field high voltage power semiconductor device, and a manufacturing method and application thereof are provided. The device includes a type I conductive semiconductor substrate, a type II conductive drift region, a type I field clamped layer, type I and type II conductive well regions, the first dielectric oxide layer forming a field oxide layer, the second dielectric oxide layer forming a gate oxide layer, a type II conductive buried dielectric layer, a type II conductive source heavily doped region, a type II conductive drain heavily doped region. The first dielectric oxide layer and the floating field plate polysilicon electrodes form a vertical floating field plate distributed throughout the type II conductive drift region to form a vertical floating equipotential field plate array. When the device is in on-state, high doping concentration can be realized by the full-region depletion effect form the vertical field plate arrays.