公开(公告)号：US20150186185A1

公开(公告)日：2015-07-02

申请号：US14657970

申请日：2015-03-13

Applicant: VMware, Inc.

Inventor： Puneet ZAROO

IPC: G06F9/50 ,  G06F12/08

CPC classification number: G06F9/48 ,  G06F9/4881 ,  G06F9/50 ,  G06F9/5005 ,  G06F9/5011 ,  G06F9/5016 ,  G06F9/5022 ,  G06F9/5027 ,  G06F9/5033 ,  G06F9/5044 ,  G06F9/505 ,  G06F9/5055 ,  G06F11/3409 ,  G06F11/3442 ,  G06F11/3452 ,  G06F11/3466 ,  G06F12/08 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0806 ,  G06F12/0815 ,  G06F12/084 ,  G06F2201/88 ,  G06F2209/483 ,  G06F2209/501

Abstract: A method includes assigning a thread performance counter to threads being created in the computing environment, the thread performance counter measuring a number of cache misses for a corresponding thread. The method also includes calculating a self-thread value S as a change in the thread performance counter of a given thread during a predetermined period, calculating an other-thread value O as a sum of changes in all the thread performance counters during the predetermined period minus S, and calculating an estimation adjustment value associated with a first probability that a second set of cache misses for the corresponding thread replace a cache area currently occupied by the corresponding thread. The method also includes estimating a cache occupancy for the thread based on a previous occupancy for the thread, S, O, and the estimation adjustment value, and assigning computing environment resources to the thread based on the estimated cache occupancy.

Abstract translation: 一种方法包括：将线程性能计数器分配给在计算环境中创建的线程，所述线程性能计数器测量相应线程的多个高速缓存未命中。 该方法还包括计算自身线程值S作为预定时间段内给定线程的线程性能计数器的变化，在预定时段内计算出所有线程性能计数器的变化之和的另一线程值O 减去S，并且计算与第一概率相关联的估计调整值，所述第一概率对于相应线程的第二组高速缓存未命中代替当前线程当前占用的高速缓存区域。 该方法还包括基于线程S，O和估计调整值的先前占用来估计线程的高速缓存占用，以及基于估计的高速缓存占用向线程分配计算环境资源。

公开(公告)号：US20130232500A1

公开(公告)日：2013-09-05

申请号：US13853734

申请日：2013-03-29

Applicant: VMWARE, INC.

Inventor： Puneet ZAROO ,  Richard WEST ,  Carl A. WALDSPURGER ,  Xiao ZHANG

IPC: G06F9/48 ,  G06F9/50

CPC classification number: G06F9/48 ,  G06F9/4881 ,  G06F9/50 ,  G06F9/5005 ,  G06F9/5011 ,  G06F9/5016 ,  G06F9/5022 ,  G06F9/5027 ,  G06F9/5033 ,  G06F9/5044 ,  G06F9/505 ,  G06F9/5055 ,  G06F11/3409 ,  G06F11/3442 ,  G06F11/3452 ,  G06F11/3466 ,  G06F12/08 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0806 ,  G06F12/0815 ,  G06F12/084 ,  G06F2201/88 ,  G06F2209/483 ,  G06F2209/501

Abstract: A method is described for scheduling in an intelligent manner a plurality of threads on a processor having a plurality of cores and a shared last level cache (LLC). In the method, a first and second scenario having a corresponding first and second combination of threads are identified. The cache occupancies of each of the threads for each of the scenarios are predicted. The predicted cache occupancies being a representation of an amount of the LLC that each of the threads would occupy when running with the other threads on the processor according to the particular scenario. One of the scenarios is identified that results in the least objectionable impacts on all threads, the least objectionable impacts taking into account the impact resulting from the predicted cache occupancies. Finally, a scheduling decision is made according to the one of the scenarios that results in the least objectionable impacts.

Abstract translation: 描述了一种以智能方式调度具有多个核的处理器上的多个线程和共享的最后一级高速缓存（LLC）的方法。 在该方法中，识别具有对应的第一和第二线程组合的第一和第二情景。 预测每个场景的每个线程的高速缓存占用。 预测的高速缓存占用是根据特定场景与处理器上的其他线程一起运行时每个线程将占用的LLC的量的表示。 确定了一种情景，对所有线程造成的影响最小，最不令人反感的影响考虑到预测的缓存占用引起的影响。 最后，根据导致最不利影响的情景之一进行调度决策。

公开(公告)号：US20170031819A1

公开(公告)日：2017-02-02

申请号：US15289893

申请日：2016-10-10

Applicant: VMware, Inc.

Inventor： Rajesh VENKATASUBRAMANIAN ,  Puneet ZAROO ,  Alexandre MILOUCHEV

IPC: G06F12/08 ,  G06F9/50 ,  G06F9/455 ,  G06F12/0811 ,  G06F12/084

CPC classification number: G06F12/08 ,  G06F3/0604 ,  G06F3/0614 ,  G06F3/0662 ,  G06F3/0665 ,  G06F9/45558 ,  G06F9/5033 ,  G06F9/5083 ,  G06F12/0292 ,  G06F12/0638 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0868 ,  G06F12/0891 ,  G06F12/10 ,  G06F12/1009 ,  G06F12/1072 ,  G06F2009/45583 ,  G06F2212/1016 ,  G06F2212/152 ,  G06F2212/2542 ,  G06F2212/6042 ,  G06F2212/62

Abstract: In a system having non-uniform memory access architecture, with a plurality of nodes, memory access by entities such as virtual CPUs is estimated by invalidating a selected sub-set of memory units, and then detecting and compiling access statistics, for example by counting the page faults that arise when any virtual CPU accesses an invalidated memory unit. The entities, or pairs of entities, may then be migrated or otherwise co-located on the node for which they have greatest memory locality.

Abstract translation: 在具有不均匀的存储器访问架构的系统中，通过多个节点，通过使所选择的存储单元的子集失效，然后检测和编译访问统计信息来估计诸如虚拟CPU之类的实体的存储器访问，例如通过计数 任何虚拟CPU访问无效内存单元时出现的页面故障。 然后可以将实体或实体对迁移或以其他方式共同位于它们具有最大存储器位置的节点上。

公开(公告)号：US20150052287A1

公开(公告)日：2015-02-19

申请号：US14201787

申请日：2014-03-07

Applicant: VMware, Inc.

Inventor： Rajesh VENKATASUBRAMANIAN ,  Puneet ZAROO ,  Alexandre MILOUCHEV

IPC: G06F3/06

CPC classification number: G06F12/08 ,  G06F3/0604 ,  G06F3/0614 ,  G06F3/0662 ,  G06F3/0665 ,  G06F9/45558 ,  G06F9/5033 ,  G06F9/5083 ,  G06F12/0292 ,  G06F12/0638 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0868 ,  G06F12/0891 ,  G06F12/10 ,  G06F12/1009 ,  G06F12/1072 ,  G06F2009/45583 ,  G06F2212/1016 ,  G06F2212/152 ,  G06F2212/2542 ,  G06F2212/6042 ,  G06F2212/62

Abstract: In a system having non-uniform memory access architecture, with a plurality of nodes, memory access by entities such as virtual CPUs is estimated by invalidating a selected sub-set of memory units, and then detecting and compiling access statistics, for example by counting the page faults that arise when any virtual CPU accesses an invalidated memory unit. The entities, or pairs of entities, may then be migrated or otherwise co-located on the node for which they have greatest memory locality.

Abstract translation: 在具有不均匀的存储器访问架构的系统中，通过多个节点，通过使所选择的存储单元的子集失效，然后检测和编译访问统计信息来估计诸如虚拟CPU之类的实体的存储器访问，例如通过计数 任何虚拟CPU访问无效内存单元时出现的页面故障。 然后可以将实体或实体对迁移或以其他方式共同位于它们具有最大存储器位置的节点上。

公开(公告)号：US20140189248A1

公开(公告)日：2014-07-03

申请号：US14196100

申请日：2014-03-04

Applicant: VMware, Inc.

Inventor： Carl A. WALDSPURGER ,  Rajesh VENKATASUBRAMANIAN ,  Alexander Thomas GARTHWAITE ,  Yury BASKAKOV ,  Puneet ZAROO

IPC: G06F12/12

CPC classification number: G06F12/122 ,  G06F9/45558 ,  G06F11/3471 ,  G06F12/123 ,  G06F2009/45583 ,  G06F2201/815 ,  G06F2201/88

Abstract: Miss rate curves are constructed in a resource-efficient manner so that they can be constructed and memory management decisions can be made while the workloads are running. The resource-efficient technique includes the steps of selecting a subset of memory pages for the workload, maintaining a least recently used (LRU) data structure for the selected memory pages, detecting accesses to the selected memory pages and updating the LRU data structure in response to the detected accesses, and generating data for constructing a miss-rate curve for the workload using the LRU data structure. After a memory page is accessed, the memory page may be left untraced for a period of time, after which the memory page is retraced.

Abstract translation: 错误率曲线以资源有效的方式构建，以便可以构建它们，并且可以在工作负载运行时进行内存管理决策。 资源有效的技术包括以下步骤：为工作负载选择存储器页面的子集，维护所选择的存储器页面的最近最少使用的（LRU）数据结构，检测对所选择的存储器页面的访问并响应更新LRU数据结构 并且使用LRU数据结构生成用于构建工作负载的错过率曲线的数据。 在访问存储器页面之后，存储器页面可以保持未被跟踪一段时间，之后再回读存储器页面。