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22 条记录 (耗时 0.042 秒)

    Method and apparatus for self identification of circuitry
    1.
    发明授权
    Method and apparatus for self identification of circuitry 有权
    用于电路自我识别的方法和装置

    公开(公告)号：US07735031B2

    公开(公告)日：2010-06-08

    申请号：US11841125

    申请日：2007-08-20

    申请人： Valerie Hornbeck Chickanosky ,  Kevin William Gorman ,  Emory D. Keller ,  Michael Richard Ouellette

    发明人： Valerie Hornbeck Chickanosky ,  Kevin William Gorman ,  Emory D. Keller ,  Michael Richard Ouellette

    IPC分类号： G06F17/50

    CPC分类号： G01R31/31724 ,  G01R31/31721

    摘要： A system that includes a controller for enabling an enumeration operation. The enumeration operation is performed by a controller (110) and logic elements (120) in a system, such that each logic element in the system assigns itself a unique identifier. Each logic element can then be controlled by another source or have a means to communicate with other logic elements in the system. The unique identifier enables greater system flexibility, thereby reducing cost and improving efficiency.

    摘要翻译： 一种包括用于启用枚举操作的控制器的系统。 枚举操作由系统中的控制器（110）和逻辑元件（120）执行，使得系统中的每个逻辑元件分配自身唯一的标识符。 然后，每个逻辑元件可以被另一个源控制，或者具有与系统中的其它逻辑元件通信的手段。 独特的标识符可以实现更大的系统灵活性，从而降低成本并提高效率。

    METHOD AND APPARATUS FOR SELF IDENTIFICATION OF CIRCUITRY
    2.
    发明申请
    METHOD AND APPARATUS FOR SELF IDENTIFICATION OF CIRCUITRY 有权
    自动识别电路的方法和装置

    公开(公告)号：US20090052609A1

    公开(公告)日：2009-02-26

    申请号：US11841125

    申请日：2007-08-20

    申请人： Valerie Hornbeck Chickanosky ,  Kevin William Gorman ,  Emory D. Keller ,  Michael Richard Ouellette

    发明人： Valerie Hornbeck Chickanosky ,  Kevin William Gorman ,  Emory D. Keller ,  Michael Richard Ouellette

    IPC分类号： G01F15/06

    CPC分类号： G01R31/31724 ,  G01R31/31721

    摘要： A system that includes a controller for enabling an enumeration operation. The enumeration operation is performed by a controller (110) and logic elements (120) in a system, such that each logic element in the system assigns itself a unique identifier. Each logic element can then be controlled by another source or have a means to communicate with other logic elements in the system. The unique identifier enables greater system flexibility, thereby reducing cost and improving efficiency.

    摘要翻译： 一种包括用于启用枚举操作的控制器的系统。 枚举操作由系统中的控制器（110）和逻辑元件（120）执行，使得系统中的每个逻辑元件分配自身唯一的标识符。 然后，每个逻辑元件可以被另一个源控制，或者具有与系统中的其它逻辑元件通信的手段。 独特的标识符可以实现更大的系统灵活性，从而降低成本并提高效率。

    Selectable repair pass masking
    3.
    发明授权
    Selectable repair pass masking 有权
    可选择修复通过掩蔽

    公开(公告)号：US08570820B2

    公开(公告)日：2013-10-29

    申请号：US13042881

    申请日：2011-03-08

    申请人： Kevin William Gorman ,  John Robert Goss ,  Michael Richard Ouellette ,  Troy Joseph Perry ,  Michael Anthony Ziegerhofer

    发明人： Kevin William Gorman ,  John Robert Goss ,  Michael Richard Ouellette ,  Troy Joseph Perry ,  Michael Anthony Ziegerhofer

    IPC分类号： G11C7/10

    CPC分类号： G11C29/4401 ,  G11C29/76 ,  G11C29/802 ,  G11C2029/0401 ,  G11C2229/726

    摘要： The present invention relates to a method and circuit for selectively repairing an embedded memory module having memory elements in an integrated circuit chip. The method includes performing a plurality of tests on the embedded memory module under operating conditions to identify a plurality of non-operational memory elements in the embedded memory module and, in response to identifying the non-operational memory elements, generating a plurality of corresponding repair solutions. The method further includes storing the plurality of corresponding repair solutions in a non-volatile storage element and determining from a mask a subset of the plurality of repair solutions that should be restored.

    摘要翻译： 本发明涉及一种用于选择性地修复在集成电路芯片中具有存储元件的嵌入式存储器模块的方法和电路。 该方法包括在操作条件下对嵌入式存储器模块执行多个测试以识别嵌入式存储器模块中的多个非操作存储器元件，并且响应于识别非操作存储器元件，生成多个相应的修复 解决方案 该方法还包括将多个相应的修复解决方案存储在非易失性存储元件中，并且从掩模确定应该被恢复的多个修复解决方案的子集。

    SELECTABLE REPAIR PASS MASKING
    4.
    发明申请
    SELECTABLE REPAIR PASS MASKING 有权
    可选修理通道掩蔽

    公开(公告)号：US20120230136A1

    公开(公告)日：2012-09-13

    申请号：US13042881

    申请日：2011-03-08

    申请人： Kevin William Gorman ,  John Robert Goss ,  Michael Richard Ouellette ,  Troy Joseph Perry ,  Michael Anthony Ziegerhofer

    发明人： Kevin William Gorman ,  John Robert Goss ,  Michael Richard Ouellette ,  Troy Joseph Perry ,  Michael Anthony Ziegerhofer

    IPC分类号： G11C29/00

    CPC分类号： G11C29/4401 ,  G11C29/76 ,  G11C29/802 ,  G11C2029/0401 ,  G11C2229/726

    摘要： The present invention relates to a method and circuit for selectively repairing an embedded memory module having memory elements in an integrated circuit chip. The method comprises performing a plurality of tests on the embedded memory module under operating conditions to identify a plurality of non-operational memory elements in the embedded memory module and, in response to identifying the non-operational memory elements, generating a plurality of corresponding repair solutions. The method further comprises storing the plurality of corresponding repair solutions in a non-volatile storage element and determining from a mask a subset of the plurality of repair solutions that should be restored.

    摘要翻译： 本发明涉及一种用于选择性地修复在集成电路芯片中具有存储元件的嵌入式存储器模块的方法和电路。 该方法包括在操作条件下对嵌入式存储器模块执行多个测试以识别嵌入式存储器模块中的多个非操作存储器元件，并且响应于识别非操作存储器元件，生成多个相应的修复 解决方案 该方法还包括将多个对应的修复解决方案存储在非易失性存储元件中，并从掩模确定应该被恢复的多个修复解决方案的子集。

    Structure for differential eFUSE sensing without reference fuses
    8.
    发明授权
    Structure for differential eFUSE sensing without reference fuses 有权
    不带参考保险丝的差分eFUSE检测结构

    公开(公告)号：US07688654B2

    公开(公告)日：2010-03-30

    申请号：US11769925

    申请日：2007-06-28

    申请人： Darren Lane Anand ,  John Atkinson Fifield ,  Michael Richard Ouellette

    发明人： Darren Lane Anand ,  John Atkinson Fifield ,  Michael Richard Ouellette

    IPC分类号： G11C11/063

    CPC分类号： G11C17/16 ,  G11C17/18

    摘要： A design structure comprising a differential fuse sensing system, which includes a fuse leg configured for introducing a sense current through an electrically programmable fuse (eFUSE) to be sensed, and a differential sense amplifier having a first input node coupled to the fuse leg and a second node coupled to a reference voltage. The fuse leg further includes a current supply device controlled by a variable reference current generator configured to generate an output signal therefrom such that the voltage on the first input node of the sense amplifier is equal to the voltage on the second input node of the sense amplifier whenever the resistance value of the eFUSE is equal to the resistance value of a programmable variable resistance device included within the variable reference current generator.

    摘要翻译： 一种设计结构，包括差分熔丝感测系统，其包括被配置用于通过要被感测的电可编程熔丝（eFUSE）引入感测电流的熔丝腿，以及具有耦合到保险丝腿的第一输入节点的差分读出放大器和 耦合到参考电压的第二节点。 保险丝腿还包括由可变参考电流发生器控制的电流供应装置，其被配置为从其产生输出信号，使得读出放大器的第一输入节点上的电压等于读出放大器的第二输入节点上的电压 每当eFUSE的电阻值等于包括在可变参考电流发生器内的可编程可变电阻器件的电阻值时。

    Method and system for determining minimum post production test time required on an integrated circuit device to achieve optimum reliability
    9.
    发明授权
    Method and system for determining minimum post production test time required on an integrated circuit device to achieve optimum reliability 有权
    用于确定集成电路设备实现最佳可靠性所需的最小后期制作测试时间的方法和系统

    公开(公告)号：US07139944B2

    公开(公告)日：2006-11-21

    申请号：US10604887

    申请日：2003-08-25

    申请人： Tange Nan Barbour ,  Thomas S. Barnett ,  Matthew Sean Grady ,  William Vincent Huott ,  Michael Richard Ouellette

    发明人： Tange Nan Barbour ,  Thomas S. Barnett ,  Matthew Sean Grady ,  William Vincent Huott ,  Michael Richard Ouellette

    IPC分类号： G11C29/00 ,  G06F11/00

    CPC分类号： G11C29/44 ,  G11C29/56008 ,  G11C2029/1208 ,  G11C2029/4402

    摘要： A method and system for determining minimum post production test time on an integrated circuit device to achieve optimal reliability of that device utilizing defect counts. The number of defective cells or active elements with defective cells (DEFECTS) on the integrated circuit device are counted and this count serves as a basis for determining the minimum test time. A higher number of DEFECTS results in longer post production testing in order to achieve optimum reliability of the integrated circuit device. The number of DEFECTS can be counted on a device internal to the integrated circuit device and made available to determine the minimum required test time. The number of DEFECTS can also be obtained external to the integrated circuit device by intercepting information routed to another device. Information provided internally and externally can also reveal the physical location of DEFECTS to further refine the minimum required test time.

    摘要翻译： 一种用于在集成电路器件上确定最小后期制作测试时间以实现利用缺陷计数的该器件的最佳可靠性的方法和系统。 对集成电路装置上的缺陷单元或缺陷单元（DEFECTS）的有缺陷单元的数量进行计数，该计数作为确定最小测试时间的基础。 更高数量的缺陷导致更长的后期测试，以实现集成电路器件的最佳可靠性。 DEFECTS的数量可以在集成电路设备内部的设备上进行计数，并可用于确定最低要求的测试时间。 还可以通过拦截路由到另一设备的信息，在集成电路设备外部获得缺陷数量。 内部和外部提供的信息还可以显示缺陷的物理位置，以进一步完善最低要求的测试时间。