公开(公告)号：US09196589B2

公开(公告)日：2015-11-24

申请号：US13845728

申请日：2013-03-18

Applicant: Xintec Inc.

Inventor： Yu-Lin Yen ,  Hsi-Chien Lin ,  Yeh-Shih Ho

IPC: H01L29/06 ,  H01L23/00 ,  H01L21/50 ,  B81C1/00 ,  B81C3/00

CPC classification number: H01L23/562 ,  B81C1/00269 ,  B81C1/00357 ,  B81C3/001 ,  B81C2201/019 ,  H01L21/50 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A stacked wafer structure includes a substrate; dams provided on the substrate and having protrusions on a surface thereof; and a wafer with recesses provided on the dam. The protrusions on the surface of the dams are wedged into the recesses of the wafer, preventing air chambers from forming between the recesses of the wafer and the dams, so that the wafer is not separated from the dams due to the presence of air chambers during subsequent packaging process. A method for stacking a wafer is also provided.

Abstract translation: 堆叠晶片结构包括基板; 堤坝设置在基板上并在其表面上具有突起; 以及设置在坝上的具有凹槽的晶片。 坝的表面上的突起楔入晶片的凹槽中，防止在晶片的凹槽和坝之间形成空气室，使得晶片由于存在气室而不与坝隔离 随后的包装过程。 还提供了一种堆叠晶片的方法。

公开(公告)号：US08951836B2

公开(公告)日：2015-02-10

申请号：US14214389

申请日：2014-03-14

Applicant: Xintec Inc.

Inventor： Yu-Lin Yen ,  Chien-Hui Chen ,  Tsang-Yu Liu ,  Long-Sheng Yeou

IPC: H01L21/44 ,  H01L21/768 ,  B81B7/00 ,  H01L23/48 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L21/76879 ,  B81B7/007 ,  B81B2207/07 ,  B81B2207/092 ,  H01L21/76805 ,  H01L21/76898 ,  H01L23/3178 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/06 ,  H01L24/13 ,  H01L24/32 ,  H01L24/94 ,  H01L25/0657 ,  H01L2221/68377 ,  H01L2224/0401 ,  H01L2224/05553 ,  H01L2224/0557 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/13025 ,  H01L2224/9202 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01021 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A method for forming a chip package, in which a substrate has a plurality of conducting pads located below its lower surface, and a dielectric layer located between the conducting pads. A hole is formed extending from the upper surface of the substrate towards the conducting pads. After the hole is formed, a trench is formed extending from the upper surface towards the lower surface of the substrate, with the trench connecting with the hole. An insulating layer is formed on a sidewall of the trench and a sidewall and a bottom of the hole, and a portion of the insulating layer and a portion of the dielectric layer are removed to expose a portion of the conducting pads. A conducting layer is formed on the sidewall of the trench and the sidewall and the bottom of the hole, electrically contacting with the conducting pads.

Abstract translation: 一种用于形成芯片封装的方法，其中衬底具有位于其下表面下方的多个导电焊盘以及位于导电焊盘之间的电介质层。 形成从衬底的上表面朝向导电垫延伸的孔。 在形成孔之后，形成从衬底的上表面向下表面延伸的沟槽，沟槽与孔连接。 绝缘层形成在沟槽的侧壁和孔的侧壁和底部上，绝缘层的一部分和电介质层的一部分被去除以暴露导电垫的一部分。 导电层形成在沟槽的侧壁和孔的侧壁和底部，与导电垫电接触。

公开(公告)号：US09236429B2

公开(公告)日：2016-01-12

申请号：US14699261

申请日：2015-04-29

Applicant: XINTEC INC.

Inventor： Yu-Lin Yen ,  Sheng-Hao Chiang ,  Hung-Chang Chen ,  Ho-Ku Lan ,  Chen-Mei Fan

IPC: H01L27/14 ,  H01L29/06 ,  H01L21/762

CPC classification number: H01L29/0642 ,  H01L21/76229 ,  H01L27/1463 ,  H01L27/14683

Abstract: A semiconductor structure includes a substrate, a dam element, a first isolation layer, a second isolation layer, and a conductive layer. The substrate has a conductive pad, a trench, a sidewall, a first surface, and a second surface opposite to the first surface. The conductive pad is located on the second surface. The trench has a first opening at the first surface, and has a second opening at the second surface. The dam element is located on the second surface and covers the second opening. The dam element has a concave portion that is at the second opening. The first isolation layer is located on a portion of the sidewall. The second isolation layer is located on the first surface and the sidewall that is not covered by the first isolation layer, such that an interface is formed between the first and second isolation layers.

Abstract translation: 半导体结构包括基板，阻挡元件，第一隔离层，第二隔离层和导电层。 衬底具有导电焊盘，沟槽，侧壁，第一表面和与第一表面相对的第二表面。 导电垫位于第二表面上。 沟槽在第一表面具有第一开口，并且在第二表面具有第二开口。 坝体元件位于第二表面并覆盖第二开口。 坝体元件具有在第二开口处的凹入部分。 第一隔离层位于侧壁的一部分上。 第二隔离层位于不被第一隔离层覆盖的第一表面和侧壁上，使得在第一和第二隔离层之间形成界面。

公开(公告)号：US09184092B2

公开(公告)日：2015-11-10

申请号：US14214408

申请日：2014-03-14

Applicant: XINTEC INC.

Inventor： Yu-Lin Yen ,  Chien-Hui Chen ,  Tsang-Yu Liu ,  Long-Sheng Yeou

IPC: H01L21/44 ,  H01L21/768 ,  B81B7/00 ,  H01L23/48 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L21/76879 ,  B81B7/007 ,  B81B2207/07 ,  B81B2207/092 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/06 ,  H01L24/32 ,  H01L24/94 ,  H01L2221/68377 ,  H01L2224/0557 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01021 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A method for forming a chip package, by providing a substrate having a plurality of conducting pads below a lower surface, and a dielectric layer located between the conducting pads, forming a recess in an upper surface of the substrate, forming a hole extending through the bottom of the recess, forming an insulating layer on the sidewall of the recess and in the hole, exposing a portion of the conducting pads through the insulating layer, and forming a conducting layer on the insulating layer and through the hole to contact with the conducting pads.

Abstract translation: 一种用于形成芯片封装的方法，通过提供在下表面下方具有多个导电焊盘的衬底以及位于导电焊盘之间的电介质层，在衬底的上表面中形成凹陷，形成贯穿 在所述凹部的所述侧壁上形成绝缘层，并且在所述孔中形成绝缘层，使所述导电焊盘的一部分通过所述绝缘层露出，并且在所述绝缘层上形成导电层，并且穿过所述孔与所述导电体 垫

公开(公告)号：US20130285215A1

公开(公告)日：2013-10-31

申请号：US13845728

申请日：2013-03-18

Applicant: XINTEC INC.

Inventor： Yu-Lin Yen ,  Hsi-Chien Lin ,  Yeh-Shih Ho

IPC: H01L23/00 ,  H01L21/50

CPC classification number: H01L23/562 ,  B81C1/00269 ,  B81C1/00357 ,  B81C3/001 ,  B81C2201/019 ,  H01L21/50 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A stacked wafer structure includes a substrate; dams provided on the substrate and having protrusions on a surface thereof; and a wafer with recesses provided on the dam. The protrusions on the surface of the dams are wedged into the recesses of the wafer, preventing air chambers from forming between the recesses of the wafer and the dams, so that the wafer is not separated from the dams due to the presence of air chambers during subsequent packaging process. A method for stacking a wafer is also provided.

Abstract translation: 堆叠晶片结构包括基板; 堤坝设置在基板上并在其表面上具有突起; 以及设置在坝上的具有凹槽的晶片。 坝的表面上的突起楔入晶片的凹槽中，防止在晶片的凹槽和坝之间形成空气室，使得晶片由于存在气室而不与坝隔离 随后的包装过程。 还提供了一种堆叠晶片的方法。