公开(公告)号：US11256648B1

公开(公告)日：2022-02-22

申请号：US17037396

申请日：2020-09-29

Applicant: XILINX, INC.

Inventor： Chuan Cheng Pan ,  Hanh Hoang ,  Chandrasekhar S. Thyamagondlu

IPC: G06F13/40 ,  G06F13/24 ,  G06F13/42

Abstract: A method for managing a pool of physical functions in a PCIe integrated endpoint includes receiving a configuration instruction indicating a topology for a PCIe connected integrated endpoint (IE), and implementing the topology on the IE. The method further includes receiving a hot plug instruction, and, based at least in part, on the hot plug instruction, adding or removing a virtual endpoint (vEP) to or from a virtual downstream port (vDSP) on the IE.

公开(公告)号：US09100015B1

公开(公告)日：2015-08-04

申请号：US14322384

申请日：2014-07-02

Applicant: Xilinx, Inc.

Inventor： Chuan Cheng Pan ,  Ashish Gupta ,  Siva Prasad Gadey

IPC: H03K19/20 ,  H03K19/21

CPC classification number: H03K19/20 ,  H03K19/21 ,  H03K19/212

Abstract: Finding the first bit that is set in an n-bit input word includes generating n n-bit patterns from an n-bit input word. If the bit at one bit position of the input word has a logic 1 value, a corresponding pattern has a logic 1 value in a corresponding bit position and in each bit position left of the corresponding bit position, and a logic 0 value in each bit position right of the corresponding bit position. If the bit at the one bit position of the input word has a logic 0 value, the corresponding pattern has a logic 0 value in every bit position. The n patterns are combined into one merged n-bit pattern. An output n-bit pattern is generated from the merged n-bit pattern. The output pattern has a logic 1 value in one bit position that is the same as the rightmost bit position of the input word having a logic 1 value, and a logic 0 value in every other bit position.

Abstract translation: 查找在n位输入字中设置的第一位包括从n位输入字生成n个n位模式。 如果输入字的一位位置的位具有逻辑1值，则对应的模式在对应位位置和相应位位置左侧的每个位位置中具有逻辑1值，并且每个位中的逻辑0值 相应位位置的右侧。 如果输入字的一位位置的位具有逻辑0值，则相应的模式在每个位的位置都有一个逻辑0值。 n个图案被组合成一个合并的n位模式。 从合并的n位模式生成输出n位模式。 输出图案在一个位位置具有与具有逻辑1值的输入字的最右边位置相同的一个位置中的逻辑1值，以及每隔一个位位置的逻辑0值。

公开(公告)号：US11196715B2

公开(公告)日：2021-12-07

申请号：US16513218

申请日：2019-07-16

Applicant: XILINX, INC.

Inventor： Anujan Varma ,  Poching Sun ,  Chuan Cheng Pan ,  Suchithra Ravi

IPC: H04L29/06 ,  G06F1/3287 ,  G06F21/60 ,  G06F21/64

Abstract: A system comprises one or more slice-aggregated cryptographic slices each configured to perform a plurality of operations on an incoming data transfer at a first processing rate by aggregating one or more individual cryptographic slices each configured to perform the plurality of operations on a portion of the incoming data transfer at a second processing rate. Each of the individual cryptographic slices comprises in a serial connection an ingress block configured to take the portion of the incoming data transfer at the second processing rate, a cryptographic engine configured to perform the operations on the portion of the incoming data transfer, an egress block configured to process a signature of the portion and output the portion of the incoming data transfer once the operations have completed. The first processing rate of each slice-aggregated cryptographic slices equals aggregated second processing rates of the individual cryptographic slices in the slice-aggregated cryptographic slice.

公开(公告)号：US10659437B1

公开(公告)日：2020-05-19

申请号：US16144705

申请日：2018-09-27

Applicant: Xilinx, Inc.

Inventor： Ravi Sunkavalli ,  Anujan Varma ,  Chuan Cheng Pan ,  Patrick C. McCarthy ,  Hanh Hoang

IPC: H04L29/06

Abstract: A circuit arrangement includes an encryption circuit and a decryption circuit. A cryptographic shell circuit has a transmit channel and a receive channel in parallel with the transmit channel. The transmit channel includes an encryption interface circuit coupled to the encryption circuit. The encryption interface circuit determines first cryptographic parameters based on data in a plaintext input packet and inputs the first cryptographic parameters and plaintext input packet to the encryption circuit. The receive channel includes a decryption interface circuit coupled to the decryption circuit. The decryption interface circuit determines second cryptographic parameters based on data in a ciphertext input packet and inputs the second cryptographic parameters and ciphertext input packet to the decryption circuit. The encryption circuit encrypts the plaintext input packet based on the first cryptographic parameters, and the decryption circuit decrypts the ciphertext input packet based on the second cryptographic parameters.