公开(公告)号：US08972920B1

公开(公告)日：2015-03-03

申请号：US14178035

申请日：2014-02-11

Applicant: Xilinx, Inc.

Inventor： Grigor S. Gasparyan ,  Dinesh D. Gaitonde ,  Yau-Tsun S. Li

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/50 ,  G06F17/5031 ,  G06F17/5054 ,  G06F2217/84

Abstract: Re-budgeting connections includes detecting a budget event for a circuit design and, responsive to detecting the budget event, calculating, using a processor, a delta for a selected combinatorial circuit element of the circuit design using an incoming slack and an outgoing slack of the selected combinatorial circuit element. Using the processor, a delay budget for a connection of the selected combinatorial circuit element is adjusted using the delta responsive to detecting the budget event.

Abstract translation: 重新预算连接包括检测用于电路设计的预算事件，并且响应于检测到预算事件，使用处理器计算电路设计的所选择的组合电路元件的增量，使用输入的松弛和输出的松弛 选择的组合电路元件。 使用处理器，使用响应于检测预算事件的增量来调整所选择的组合电路元件的连接的延迟预算。

公开(公告)号：US10853541B1

公开(公告)日：2020-12-01

申请号：US16399661

申请日：2019-04-30

Applicant: Xilinx, Inc.

Inventor： Abhishek Joshi ,  Grigor S. Gasparyan ,  Aditya Chaubal ,  Sridhar Kirshnamurthy ,  Xiao Dong

IPC: G06F30/327 ,  G06F30/331 ,  G06F30/34 ,  G06F13/40 ,  G06F15/78

Abstract: Some examples described herein relate to global mapping of program nodes of a netlist of an application. In an example, a design system includes a processor and a memory coupled to the processor. The memory stores instruction code. The processor is configured to execute the instruction code to obtain a netlist of an application. The netlist contains program nodes and respective edges between the program nodes. The application is to be implemented on a device comprising an array of data processing engines. The processor is also configured to execute the instruction code to generate a global mapping of the program nodes based on a representation of the array of data processing engines and using an integer linear programming (ILP) algorithm; generate a detailed mapping of the program nodes based on the global mapping; and translate the detailed mapping to a file.

公开(公告)号：US08959474B1

公开(公告)日：2015-02-17

申请号：US14243813

申请日：2014-04-02

Applicant: Xilinx, Inc.

Inventor： Grigor S. Gasparyan ,  Garik Mkrtchyan

IPC: G06F17/50

CPC classification number: G06F17/5077

Abstract: Routing a multi-fanout net includes selecting a driver component of the multi-fanout net of a circuit design, wherein the circuit design is specified programmatically, and determining a plurality of targets of the driver component. A source wave is created at each of a plurality of nodes of the driver component. One target is assigned to each source wave. Each source wave is expanded.

Abstract translation: 路由多扇出网包括选择电路设计的多扇出网络的驱动器组件，其中电路设计以编程方式指定，并且确定驱动器组件的多个目标。 在驱动器部件的多个节点中的每一个处产生源波。 一个目标被分配给每个源波。 每个源波都被扩展。

公开(公告)号：US11238206B1

公开(公告)日：2022-02-01

申请号：US17213474

申请日：2021-03-26

Applicant: Xilinx, Inc.

Inventor： Satish B. Sivaswamy ,  Nitin Deshmukh ,  Garik Mkrtchyan ,  Grigor S. Gasparyan

IPC: G06F30/392 ,  G06F30/3312 ,  G06F30/327 ,  G06F30/373 ,  G06F30/3953 ,  G06F30/3947 ,  G06F30/398

Abstract: Performing partition wire assignment for routing a multi-partition circuit design can include performing, using computer hardware, a global assignment phase by clustering a plurality of super-long lines (SLLs) into a plurality of SLL bins, clustering loads of nets of a circuit design into a plurality of load clusters, and assigning the plurality of SLL bins to the plurality of load clusters. For each SLL bin, a detailed assignment phase can be performed wherein each net having a load cluster assigned to the SLL bin is assigned one or more particular SLLs of the SLL bin using the computer hardware.

公开(公告)号：US10108773B1

公开(公告)日：2018-10-23

申请号：US15350957

申请日：2016-11-14

Applicant: Xilinx, Inc.

Inventor： Grigor S. Gasparyan ,  Xiao Dong ,  Xiaojian Yang

IPC: G06F17/50

Abstract: Partitioning a circuit design can include determining, using a processor, a target area utilization and a target cut utilization by iterating over a range of timing violations and determining, using the processor, a worst allowed timing violation based upon the target area utilization and the target cut utilization. Circuit elements of the circuit design can be assigned to partitions, using the processor, for implementation of the circuit design in a multi-die integrated circuit based upon a partition cost calculated using the target area utilization, the target cut utilization, and the worst allowed timing violation.

公开(公告)号：US10963615B1

公开(公告)日：2021-03-30

申请号：US16399445

申请日：2019-04-30

Applicant: Xilinx, Inc.

Inventor： Abhishek Joshi ,  Grigor S. Gasparyan

IPC: G06F30/394 ,  H03K19/1776 ,  H03K19/17736 ,  G06F30/33 ,  G06F30/327

Abstract: Some examples described herein relate to routing in routing elements. In an example, a design system includes a processor and a memory, storing instruction code, coupled to the processor. The processor is configured to execute the instruction code to model a communication network comprising switches interconnected in an array of data processing engines (DPEs), generate global routes of nets in the modeled communication network, generate detailed routes of the nets using the global routes, and translate the detailed routes to a file. Each of the switches has multiple input or output channels connected to another switch that are modeled as a single input or output edge, respectively, connected to the other switch. Each global route is generated through edge(s) of the switches. Each detailed route is generated comprising identifying one of the multiple input or output channels modeled by each edge through which the respective global route is generated.

公开(公告)号：US10891413B1

公开(公告)日：2021-01-12

申请号：US16704762

申请日：2019-12-05

Applicant: Xilinx, Inc.

Inventor： Paul D. Kundarewich ,  Grigor S. Gasparyan ,  Mehrdad Eslami Dehkordi ,  Guenter Stenz

IPC: G06F30/333 ,  G06F30/392 ,  G06F30/327 ,  G06F111/04

Abstract: Disclosed approaches for processing a circuit design include providing access to checkpoint data of a design checkpoint of a circuit design and starting child processes by a parent process. An initial intermediate representation is generated by the parent process, and concurrent with the generating of the initial intermediate representation, the child processes load the checkpoint data into respective memory spaces. The parent process produces incremental updates to the design checkpoint. The parent process signals availability of the incremental updates to the child processes, which apply the incremental updates to the checkpoint data in the respective memory spaces. The child processes process the circuit design in response to completion of producing incremental updates by the parent placer process.

公开(公告)号：US10366201B1

公开(公告)日：2019-07-30

申请号：US15495760

申请日：2017-04-24

Applicant: Xilinx, Inc.

Inventor： Aaron Ng ,  Sridhar Krishnamurthy ,  Grigor S. Gasparyan

IPC: G06F9/455 ,  G06F17/50

Abstract: Closing timing for a circuit design can include displaying, using a display device, a first region having a plurality of controls corresponding to a plurality of data sets generated at different times during a phase of a design flow for a circuit design, wherein each control selects a data set associated with the control, and displaying, using the display device, a second region configured to display a list of critical paths for data sets selected from the first region using one of the plurality of controls. Closing timing further can include displaying, using the display device, a third region configured to display a representation of a target integrated circuit including layouts for the critical paths of the list for implementations of the circuit design specified by the selected data sets.

公开(公告)号：US09529957B1

公开(公告)日：2016-12-27

申请号：US14606988

申请日：2015-01-27

Applicant: Xilinx, Inc.

Inventor： Grigor S. Gasparyan ,  Xiao Dong ,  Marvin Tom

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5054

Abstract: Placing a circuit design may include partitioning circuit elements of the circuit design into circuit element sets and grouping bins of an integrated circuit into bin sets. The bins include circuit elements of the circuit design from an initial placement. Placing a circuit design also may include determining a dependency connectivity metric for the circuit elements and, using a processor, selectively relocating circuit elements concurrently, for a plurality of iterations, using a cost metric for relocating the circuit elements and using an order of processing the circuit elements determined from the bin sets, the circuit element sets, and the dependency connectivity metrics.

Abstract translation: 放置电路设计可以包括将电路设计的电路元件分成电路元件组，并将集成电路的盒分组成箱组。 该箱包括从初始放置的电路设计的电路元件。 放置电路设计还可以包括确定电路元件的依赖性连接度量，并且使用处理器，使用用于重新定位电路元件的成本度量并使用处理顺序来选择性地重新定位电路元件，用于多个迭代 从箱组确定的电路元件，电路元件组和依赖性连接度量。

公开(公告)号：US11106851B1

公开(公告)日：2021-08-31

申请号：US16805604

申请日：2020-02-28

Applicant: Xilinx, Inc.

Inventor： Paul D. Kundarewich ,  Grigor S. Gasparyan ,  Mehrdad Eslami Dehkordi ,  Guenter Stenz ,  Xiao Dong

IPC: G06F30/392

Abstract: Disclosed approaches for processing a circuit design include interrupting processing of a circuit design by an electronic design automation (EDA) tool at a selected phase of processing. The tool serializes EDA state data into serialized state data while processing is interrupted and writes the serialized state data for subsequent restoration of tool state. To resume processing at the point of interruption, the EDA tool can read the serialized state data and deserialize the serialized state data. The EDA tool bypasses one or more phases of processing after reading the serialized state data and thereafter resumes processing of the circuit design.