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公开(公告)号：US20240196632A1
公开(公告)日：2024-06-13
申请号：US18148849
申请日：2022-12-30
发明人： Sheng Peng , Zhiyong Lu , Wenbo Zhang , Xiaoming Mao , Zhaohui Cheng , Jing Gao , Lei Xue
IPC分类号： H10B80/00
CPC分类号： H10B80/00
摘要： Semiconductor components, fabrication methods thereof and memory systems. A fabrication method includes performing trap repairing on a first wafer at a first temperature, the first wafer including memory cells; bonding the first wafer with a second wafer to form a semiconductor component, the second wafer including a device layer; and repairing the semiconductor component at a second temperature lower than the first temperature.
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2.发明授权公开(公告)号：US11456315B2
公开(公告)日：2022-09-27
申请号：US16909566
申请日：2020-06-23
发明人： Feng Lu , Jing Gao , Wenbin Zhou
IPC分类号： H01L27/11582 , H01L27/1157 , H01L27/11565
摘要： A method for forming a three-dimensional (3D) memory device is disclosed. In some embodiments, the method includes forming an alternating dielectric stack on a substrate, and forming a plurality of channel holes penetrating the alternating dielectric stack vertically to expose at least a portion of the substrate. A first mask can be formed to cover the channel holes in a first area and expose the channel holes in a second area. The method also includes forming a recess in the alternating dielectric stack in the second area, followed by forming a second mask in the recess. The second mask covers the channel holes in the second area and exposes the channel holes in the first area. The memory film at bottom of each channel hole in the first area can therefore be removed, while the memory film in the second area can be protected by the second mask.
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公开(公告)号：US20210104540A1
公开(公告)日：2021-04-08
申请号：US17100841
申请日：2020-11-21
发明人： Bo Xu , Ping Yan , Chuan Yang , Jing Gao , Zongliang Huo , Lu Zhang
IPC分类号： H01L27/11582 , H01L21/02 , H01L23/522 , H01L23/528 , H01L23/532 , H01L27/11565 , H01L29/10
摘要： Embodiments of a three-dimensional (3D) memory device with a corrosion-resistant composite spacer and method for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A dielectric stack including a plurality of dielectric/sacrificial layer pairs is formed on a substrate. A memory string extending vertically through the dielectric stack is formed. A slit extending vertically through the dielectric stack is formed. A memory stack is formed on the substrate including a plurality of conductor/dielectric layer pairs by replacing, with a plurality of conductor layers, the sacrificial layers in the dielectric/sacrificial layer pairs through the slit. A composite spacer is formed along a sidewall of the slit. The composite spacer includes a first silicon oxide film, a second silicon oxide film, and a dielectric film formed laterally between the first silicon oxide film and the second silicon oxide film. A slit contact extending vertically in the slit is formed.
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公开(公告)号：US11594552B2
公开(公告)日：2023-02-28
申请号：US17100841
申请日：2020-11-21
发明人： Bo Xu , Ping Yan , Chuan Yang , Jing Gao , Zongliang Huo , Lu Zhang
IPC分类号： H01L29/51 , H01L27/11582 , H01L21/02 , H01L23/522 , H01L23/528 , H01L23/532 , H01L27/11565 , H01L29/10 , H01L21/28 , H01L21/768
摘要： Embodiments of a three-dimensional (3D) memory device with a corrosion-resistant composite spacer and method for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A dielectric stack including a plurality of dielectric/sacrificial layer pairs is formed on a substrate. A memory string extending vertically through the dielectric stack is formed. A slit extending vertically through the dielectric stack is formed. A memory stack is formed on the substrate including a plurality of conductor/dielectric layer pairs by replacing, with a plurality of conductor layers, the sacrificial layers in the dielectric/sacrificial layer pairs through the slit. A composite spacer is formed along a sidewall of the slit. The composite spacer includes a first silicon oxide film, a second silicon oxide film, and a dielectric film formed laterally between the first silicon oxide film and the second silicon oxide film. A slit contact extending vertically in the slit is formed.
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公开(公告)号：US20210118891A1
公开(公告)日：2021-04-22
申请号：US17112045
申请日：2020-12-04
发明人： Lei DING , Jing Gao , Chuan Yang , Lan Fang Yu , Ping Yan , Sen Zhang , Bo Xu
IPC分类号： H01L27/1157 , H01L27/11524 , H01L27/11556 , H01L27/11582
摘要： A method for forming a gate structure of a 3D memory device is provided. The method comprises: forming, on a substrate, an alternating dielectric stack including a plurality of dielectric layer pairs, each of the plurality of dielectric layer pairs comprising a first dielectric layer and a second dielectric layer different from the first dielectric layer; forming a slit penetrating vertically through the alternating dielectric stack and extending in a horizontal direction; removing the plurality of second dielectric layers in the alternating dielectric stack through the slit to form a plurality of horizontal trenches; forming a gate structure in each of the plurality of horizontal trenches; forming a spacer layer on sidewalls of the slit to cover the gate structures, wherein the spacer layer has a laminated structure; and forming a conductive wall in the slit, wherein the conductive wall is insulated from the gate structures by the spacer layer.
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公开(公告)号：US20200035700A1
公开(公告)日：2020-01-30
申请号：US16137628
申请日：2018-09-21
发明人： Bo Xu , Ping Yan , Chuan Yang , Jing Gao , Zongliang Huo , Lu Zhang
IPC分类号： H01L27/11582 , H01L23/522 , H01L23/532 , H01L29/10 , H01L21/02 , H01L27/11565 , H01L23/528
摘要： Embodiments of a three-dimensional (3D) memory device with a corrosion-resistant composite spacer and method for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack disposed on the substrate and including a plurality of conductor/dielectric layer pairs, a plurality of memory strings each extending vertically through the memory stack, a slit contact disposed laterally between the plurality of memory strings, and a composite spacer disposed laterally between the slit contact and at least one of the memory strings. The composite spacer includes a first silicon oxide film, a second silicon oxide film, and a dielectric film disposed laterally between the first silicon oxide film and the second silicon oxide film.
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公开(公告)号：US20240170424A1
公开(公告)日：2024-05-23
申请号：US18078898
申请日：2022-12-09
发明人： Kun Zhang , Wenxi Zhou , Jing Gao , Zhiliang Xia , Zongliang Huo
IPC分类号： H01L23/00 , H01L25/00 , H01L25/065 , H01L25/18
CPC分类号： H01L24/08 , H01L24/80 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L2224/08145 , H01L2224/80895 , H01L2224/80896 , H01L2924/1431 , H01L2924/14511
摘要： Three-dimensional (3D) memory devices and fabricating methods thereof are disclosed. In certain aspects, a method for forming a 3D memory device can comprise forming a first semiconductor structure, comprising forming a stack structure on a first substrate, and forming a gate line slit structure including a filling structure penetrating the stack structure and extending into the first substrate. The method can further comprise forming a second semiconductor structure including a periphery circuit on a second substrate, and bonding the second semiconductor structure to the first semiconductor structure. The method can further comprise removing a portion of the first substrate and a portion of the gate line slit structure extended into the first substrate, and forming a supplemental semiconductor layer on a remaining portion of the first substrate.
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公开(公告)号：US11469248B2
公开(公告)日：2022-10-11
申请号：US17112496
申请日：2020-12-04
发明人： Lei Ding , Jing Gao , Chuan Yang , Lan Fang Yu , Ping Yan , Sen Zhang , Bo Xu
IPC分类号： H01L27/11582 , H01L27/1157 , H01L27/11524 , H01L27/11556
摘要： A three-dimensional (3D) NAND memory device is provided. The device comprises an alternating stack including a plurality of dielectric/conductive layer pairs each comprising a dielectric layer and a conductive layer. The device further comprises a conductive wall vertically penetrating through the alternating stack and extending in a horizontal direction, and a spacer layer on sidewalls of the conductive wall configured to insulate the conductive wall from the conductive layers of the alternating stack. The spacer layer comprises a first spacer sublayer having a first dielectric material, a second spacer sublayer having a second dielectric material, and a third spacer sublayer having a third dielectric material. The second spacer is sandwiched between the first spacer sublayer and the third spacer sublayer. A second k-value of the second dielectric material is higher than a first k-value of the first dielectric material and higher than a third k-value of the third dielectric material.
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公开(公告)号：US20240206167A1
公开(公告)日：2024-06-20
申请号：US18208687
申请日：2023-06-12
发明人： Wenbo Zhang , Kai Yu , Zhiyong Lu , Sheng Peng , Zhaohui Cheng , Zhangyi Li , Jing Gao , Lei Xue
摘要： Three-dimensional (3D) memory devices and methods for forming the same are disclosed. In certain aspects, a 3D memory device includes a first semiconductor structure including alternating first dielectric layers and first conductive layers, an array common source (ACS) film over the first semiconductor structure, a second semiconductor structure over the ACS film, and a channel structure extending in the first semiconductor structure, the ACS film, and the second semiconductor structure in a first direction. The second semiconductor structure includes alternating second dielectric layers and second conductive layers. The channel structure is electrically connected to the ACS film.
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公开(公告)号：US11476277B2
公开(公告)日：2022-10-18
申请号：US17112045
申请日：2020-12-04
发明人： Lei Ding , Jing Gao , Chuan Yang , Lan Fang Yu , Ping Yan , Sen Zhang , Bo Xu
IPC分类号： H01L27/1157 , H01L27/11582 , H01L27/11524 , H01L27/11556
摘要： A method for forming a gate structure of a 3D memory device is provided. The method comprises: forming, on a substrate, an alternating dielectric stack including a plurality of dielectric layer pairs, each of the plurality of dielectric layer pairs comprising a first dielectric layer and a second dielectric layer different from the first dielectric layer; forming a slit penetrating vertically through the alternating dielectric stack and extending in a horizontal direction; removing the plurality of second dielectric layers in the alternating dielectric stack through the slit to form a plurality of horizontal trenches; forming a gate structure in each of the plurality of horizontal trenches; forming a spacer layer on sidewalls of the slit to cover the gate structures, wherein the spacer layer has a laminated structure; and forming a conductive wall in the slit, wherein the conductive wall is insulated from the gate structures by the spacer layer.
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