公开(公告)号：US06406982B2

公开(公告)日：2002-06-18

申请号：US09870705

申请日：2001-06-01

申请人： Yasushi Urakami ,  Shoichi Yamauchi ,  Toshio Sakakibara ,  Hitoshi Yamaguchi ,  Nobuhiro Tsuji

发明人： Yasushi Urakami ,  Shoichi Yamauchi ,  Toshio Sakakibara ,  Hitoshi Yamaguchi ,  Nobuhiro Tsuji

IPC分类号： H01L2120

CPC分类号： H01L21/763 ,  H01L21/30608 ,  H01L21/761

摘要： A trench is formed in a semiconductor substrate through a mask composed of a silicon oxide film formed on the semiconductor substrate. Then, an edge portion at an opening portion of the mask is etched so that an opening width thereof is wider than that of the trench. After that, an inner surface of the trench is smoothed by thermal treatment around at 1000° C. in non-oxidizing or non-nitriding atmosphere under low pressure. Then, the trench is filled with an epitaxial film. After that, the epitaxial film is polished, whereby a semiconductor substrate for forming a semiconductor device is obtained.

摘要翻译： 通过由形成在半导体衬底上的氧化硅膜构成的掩模，在半导体衬底中形成沟槽。 然后，蚀刻掩模的开口部分的边缘部分，使得其开口宽度比沟槽的宽度宽。 之后，通过在低压下在非氧化或非氮化气氛中在1000℃左右的热处理使沟槽的内表面平滑化。 然后，沟槽填充有外延膜。 之后，对该外延膜进行研磨，得到半导体装置的半导体基板。

公开(公告)号：US07063751B2

公开(公告)日：2006-06-20

申请号：US10132298

申请日：2002-04-26

申请人： Yasushi Urakami ,  Shoichi Yamauchi ,  Hitoshi Yamaguchi ,  Nobuhiro Tsuji

发明人： Yasushi Urakami ,  Shoichi Yamauchi ,  Hitoshi Yamaguchi ,  Nobuhiro Tsuji

IPC分类号： H01L29/12 ,  H01L29/30 ,  H01L21/20 ,  H01L21/36 ,  H01L29/04

CPC分类号： H01L21/763 ,  H01L21/30608 ,  H01L21/761

摘要： A trench is formed in a semiconductor substrate through a mask composed of a silicon oxide film formed on the semiconductor substrate. Then, an edge portion at an opening portion of the mask is etched so that the width of the mask opening width is greater than the width of the trench. After that, the inner surface of the trench is smoothed by thermal treatment around at 1000° C. in non-oxidizing or non-nitriding atmosphere under low pressure. Then, the trench is filled with an epitaxial film. After that, the epitaxial film is polished to complete the substrate.

摘要翻译： 通过由形成在半导体衬底上的氧化硅膜构成的掩模，在半导体衬底中形成沟槽。 然后，蚀刻掩模的开口部分的边缘部分，使得掩模开口宽度的宽度大于沟槽的宽度。 之后，通过在低压下在非氧化或非氮化气氛中在1000℃左右的热处理使沟槽的内表面平滑化。 然后，沟槽填充有外延膜。 之后，抛光外延膜以完成基板。

公开(公告)号：US20050045996A1

公开(公告)日：2005-03-03

申请号：US10950423

申请日：2004-09-28

申请人： Shoichi Yamauchi ,  Hitoshi Yamaguchi ,  Jun Sakakibara ,  Nobuhiro Tsuji

发明人： Shoichi Yamauchi ,  Hitoshi Yamaguchi ,  Jun Sakakibara ,  Nobuhiro Tsuji

IPC分类号： H01L21/20 ,  H01L21/336 ,  H01L29/04 ,  H01L29/06 ,  H01L29/12 ,  H01L29/423 ,  H01L29/78 ,  H01L21/332 ,  H01L31/036

CPC分类号： H01L29/781 ,  H01L29/045 ,  H01L29/0634 ,  H01L29/4232 ,  H01L29/4238 ,  H01L29/66674 ,  H01L29/7801 ,  H01L29/7813

摘要： A semiconductor device includes a semiconductor substrate and a semiconductor layer. The semiconductor substrate has a main surface that is an Si{100} surface. The substrate has a trench in the main surface. The semiconductor layer is located on surfaces defining the trench to have common crystallographic planes with the semiconductor substrate. The trench is defined by a bottom surface, two long sidewall surfaces that face each other, and two short sidewall surfaces that face each other. The bottom surface and the long sidewall surfaces are Si{100} surfaces.

摘要翻译： 半导体器件包括半导体衬底和半导体层。 半导体衬底具有作为Si {100}表面的主表面。 基板在主表面具有沟槽。 半导体层位于限定沟槽的表面上，以与半导体衬底具有共同的结晶平面。 沟槽由底面，彼此面对的两个长侧壁表面和彼此相对的两个短侧壁表面限定。 底表面和长侧壁表面是Si {100}表面。

公开(公告)号：US06836001B2

公开(公告)日：2004-12-28

申请号：US10442196

申请日：2003-05-21

申请人： Shoichi Yamauchi ,  Hitoshi Yamaguchi ,  Jun Sakakibara ,  Nobuhiro Tsuji

发明人： Shoichi Yamauchi ,  Hitoshi Yamaguchi ,  Jun Sakakibara ,  Nobuhiro Tsuji

IPC分类号： H01L2904

CPC分类号： H01L29/781 ,  H01L29/045 ,  H01L29/0634 ,  H01L29/4232 ,  H01L29/4238 ,  H01L29/66674 ,  H01L29/7801 ,  H01L29/7813

摘要： A semiconductor device includes a semiconductor substrate and a semiconductor layer. The semiconductor substrate has a main surface that is an Si{100} surface. The substrate has a trench in the main surface. The semiconductor layer is located on surfaces defining the trench to have common crystallographic planes with the semiconductor substrate. The trench is defined by a bottom surface, two long sidewall surfaces that face each other, and two short sidewall surfaces that face each other. The bottom surface and the long sidewall surfaces are Si{100} surfaces.

摘要翻译： 半导体器件包括半导体衬底和半导体层。 半导体衬底具有作为Si {100}表面的主表面。 基板在主表面具有沟槽。 半导体层位于限定沟槽的表面上，以与半导体衬底具有共同的结晶平面。 沟槽由底面，彼此面对的两个长侧壁表面和彼此相对的两个短侧壁表面限定。 底表面和长侧壁表面是Si {100}表面。

公开(公告)号：US20080211063A1

公开(公告)日：2008-09-04

申请号：US12071927

申请日：2008-02-28

申请人： Shinichi Adachi ,  Nobuhiro Tsuji ,  Shoichi Yamauchi

发明人： Shinichi Adachi ,  Nobuhiro Tsuji ,  Shoichi Yamauchi

IPC分类号： H01L23/544 ,  H01L21/20

CPC分类号： H01L21/3043 ,  H01L21/31662 ,  H01L21/78 ,  H01L23/544 ,  H01L29/0634 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor wafer includes a semiconductor substrate, a semiconductor layer, and an oxide layer. The semiconductor layer is disposed on a surface of the semiconductor substrate and has a crystal structure similar to a crystal structure of the semiconductor substrate. The semiconductor layer includes an element section and a scribe section. The scribe section is disposed to divide the element section into a plurality of portions and is configurated to be used as a cutting allowance for dicing. Each of the portions includes a column structure in which columns having different conductivity types are arranged alternately. The oxide layer is disposed on a surface of the scribe section to be exposed to an outside of the semiconductor device.

摘要翻译： 半导体晶片包括半导体衬底，半导体层和氧化物层。 半导体层设置在半导体衬底的表面上，具有与半导体衬底的晶体结构类似的晶体结构。 半导体层包括元件部分和划线部分。 划片部分设置成将元件部分分成多个部分，并且被配置为用作切割的切割余量。 这些部分中的每一个都包括具有不同导电类型的列交替布置的列结构。 氧化物层设置在划线部分的表面上以暴露于半导体器件的外部。

公开(公告)号：US07026248B2

公开(公告)日：2006-04-11

申请号：US10347190

申请日：2003-01-21

申请人： Shoichi Yamauchi ,  Nobuhiro Tsuji

发明人： Shoichi Yamauchi ,  Nobuhiro Tsuji

IPC分类号： H01L21/302

CPC分类号： H01L29/7801 ,  H01L21/3247 ,  H01L29/66674 ,  H01L29/7809 ,  H01L29/7813

摘要： In a method for manufacturing a semiconductor device of the present invention, a portion of a first epitaxial layer formed in a trench in a silicon substrate is removed by vapor phase etching using a halogenated compound or hydrogen. In this removing process, the portion of the first epitaxial layer is removed at a predetermined temperature higher than that during epitaxial growth of the first epitaxial layer and at a predetermined pressure higher than that during epitaxial growth of the first epitaxial layer. Therefore, stress that would otherwise be concentrated at a bottom portion of the trench is relaxed because rearrangement of the silicon atoms increases.

公开(公告)号：US08835276B2

公开(公告)日：2014-09-16

申请号：US12964141

申请日：2010-12-09

申请人： Syouji Nogami ,  Tomonori Yamaoka ,  Shoichi Yamauchi ,  Nobuhiro Tsuji ,  Toshiyuki Morishita

发明人： Syouji Nogami ,  Tomonori Yamaoka ,  Shoichi Yamauchi ,  Nobuhiro Tsuji ,  Toshiyuki Morishita

IPC分类号： H01L21/76 ,  H01L23/544 ,  H01L29/06 ,  H01L29/66 ,  H01L21/02

CPC分类号： H01L21/30604 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/02664 ,  H01L21/308 ,  H01L23/544 ,  H01L29/0634 ,  H01L29/66712 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10S438/975 ,  H01L2924/00

摘要： A semiconductor substrate is provided in which an alignment mark is formed that can be used for an alignment even after the formation of an impurity diffused layer by the planarization of an epitaxial film. A trench is formed in an alignment region of an N+-type substrate. This trench is used to leave voids after the formation of an N−-type layer. Then, the voids formed in the N+-type substrate can be used as an alignment mark. Thus, such a semiconductor substrate can be used to provide an alignment in the subsequent step of manufacturing the semiconductor apparatus. Thus, the respective components constituting the semiconductor apparatus can be formed at desired positions accurately.

摘要翻译： 提供了一种半导体衬底，其中形成了即使在通过外延膜的平坦化形成杂质扩散层之后也可以用于取向的对准标记。 在N +型衬底的取向区域中形成沟槽。 这种沟槽用于在形成N型层之后留下空隙。 然后，可以使用形成在N +型衬底中的空隙作为对准标记。 因此，可以使用这样的半导体衬底在制造半导体器件的后续步骤中提供对准。 因此，能够精确地形成构成半导体装置的各个部件。

公开(公告)号：US20090273102A1

公开(公告)日：2009-11-05

申请号：US12089497

申请日：2006-10-05

申请人： Syouji Nogami ,  Tomonori Yamaoka ,  Shoichi Yamauchi ,  Nobuhiro Tsuji ,  Toshiyuki Morishita

发明人： Syouji Nogami ,  Tomonori Yamaoka ,  Shoichi Yamauchi ,  Nobuhiro Tsuji ,  Toshiyuki Morishita

IPC分类号： H01L23/544 ,  H01L21/308

CPC分类号： H01L21/30604 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/02664 ,  H01L21/308 ,  H01L23/544 ,  H01L29/0634 ,  H01L29/66712 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10S438/975 ,  H01L2924/00

摘要： A semiconductor substrate is provided in which an alignment mark is formed that can be used for an aligment even after the formation of an impurity diffused layer by the planarization of an epitaxial film.A trench 11 is formed in an alignment region of an N+-type substrate 1. This trench 11 is used to leave voids 3 after the formation of an N−-type layer 2. Then, the voids 3 formed in the N+-type substrate 1 can be used as an alignment mark. Thus, such a semiconductor substrate can be used to provide an alignment in the subsequent step of manufacturing the semiconductor apparatus. Thus, the respective components constituting the semiconductor apparatus can be formed at desired positions accurately.

摘要翻译： 提供了一种半导体衬底，其中形成了即使在通过外延膜的平坦化形成杂质扩散层之后也可用于分配的对准标记。 在N +型衬底1的取向区域中形成沟槽11.在形成N型层2之后，该沟槽11用于留下空隙3.然后，形成在N +型衬底中的空隙3 1可用作对准标记。 因此，可以使用这样的半导体衬底在制造半导体器件的后续步骤中提供对准。 因此，能够精确地形成构成半导体装置的各个部件。

公开(公告)号：US20060046146A1

公开(公告)日：2006-03-02

申请号：US11208788

申请日：2005-08-23

申请人： Nobuhiro Tsuji ,  Hisanori Sugimoto

发明人： Nobuhiro Tsuji ,  Hisanori Sugimoto

IPC分类号： H01M4/62 ,  H01M4/50 ,  C01B31/04

CPC分类号： H01M4/625 ,  C01B32/20 ,  C01P2004/61 ,  C01P2006/11 ,  C01P2006/12 ,  H01M4/06 ,  H01M4/50

摘要： There is provided a new type of non-expanded graphite powder by peeling off a lamination plane within non-expanded graphite particles, which is useful as a conductive carbon material in a positive electrode mix for an alkaline manganese battery. The alkaline manganese battery has an excellent discharge property when the above non-expanded graphite powder are used as the conductive carbon material.

摘要翻译： 通过在非膨胀石墨颗粒内剥离层压平面来提供新型的非膨胀石墨粉末，其可用作碱性锰电池正极混合物中的导电碳材料。 当使用上述非膨胀石墨粉末作为导电碳材料时，碱锰电池具有优异的放电性能。

公开(公告)号：US20080213589A1

公开(公告)日：2008-09-04

申请号：US12073157

申请日：2008-02-29

申请人： Kenichi Hanazaki ,  Satoru Yoshinaga ,  Nobuhiro Tsuji

发明人： Kenichi Hanazaki ,  Satoru Yoshinaga ,  Nobuhiro Tsuji

IPC分类号： B32B15/02 ,  B05B5/12

CPC分类号： B21C23/26 ,  B21C1/00 ,  B21C37/042 ,  Y10T428/2964

摘要： An element wire, an electric wire including the element wire or the element wires, and a process for producing an element wire are provided, by which ductility of a core wire consisting of the element wires can be improved. The element wire is made of metal, at least one element wire being coated with an electrically insulating coating so as to constitute an electric wire. The crystal grains constituting the entire element wire are fine isometric grains. In the process for producing the element wire, an electrically conductive material is subjected to drawing so as to reduce a diameter of the material and subsequently subjected to successive bending along a longitudinal direction of the material.

摘要翻译： 提供元件线，包括元件线或元件线的电线，以及用于制造元件线的工艺，由此可以提高由元件线构成的芯线的延展性。 元件线由金属制成，至少一个元件线被电绝缘涂层涂覆以构成电线。 构成整个元件线的晶粒是细小的等轴晶粒。 在制造元件线的过程中，对导电材料进行拉伸，以减小材料的直径，随后沿材料的纵向连续弯曲。