公开(公告)号：US06535427B1

公开(公告)日：2003-03-18

申请号：US09707983

申请日：2000-11-08

申请人： Yoshinori Takano ,  Toru Tanzawa ,  Tadayuki Taura

发明人： Yoshinori Takano ,  Toru Tanzawa ,  Tadayuki Taura

IPC分类号： G11C1626

CPC分类号： G11C7/12 ,  G11C7/20 ,  G11C16/24 ,  G11C16/26

摘要： A memory cell is connected to a cell-based bit line. The cell-based bit line is connected to a bit line via a Y decoder. The bit line is connected to a sense bit line via a separation circuit. This sense bit line is connected to a sense line via a bias circuit. An amplifier circuit amplifies a signal voltage on the sense line together with a reference voltage for sensing data. The sense line is connected with a sense line initialization circuit for setting the sense line to a specified voltage. The bit line is connected with a bit line initialization circuit for setting the bit line to a specified voltage. Both the sense line initialization circuit and the bit line initialization circuit are activated in a given period before the amplifier circuit operates to sense data. Thus, the sense line and the bit line are set to specified voltages.

摘要翻译： 存储单元连接到基于单元的位线。 基于单元的位线通过Y解码器连接到位线。 位线通过分离电路连接到感测位线。 该感测位线通过偏置电路连接到感测线。 放大器电路将感测线上的信号电压与用于感测数据的参考电压一起放大。 感测线与感测线初始化电路连接，用于将感测线设置为指定电压。 位线与位线初始化电路连接，用于将位线设置为指定电压。 感测线初始化电路和位线初始化电路在放大器电路操作以感测数据之前的给定时间段内被激活。 因此，感测线和位线被设定为规定的电压。

公开(公告)号：US06807097B2

公开(公告)日：2004-10-19

申请号：US10661571

申请日：2003-09-15

申请人： Yoshinori Takano ,  Tadayuki Taura ,  Toru Tanzawa

发明人： Yoshinori Takano ,  Tadayuki Taura ,  Toru Tanzawa

IPC分类号： G11C1604

CPC分类号： G11C16/3472 ,  G11C11/5621 ,  G11C11/5642 ,  G11C16/28 ,  G11C16/3436 ,  G11C16/3481 ,  G11C2211/5621 ,  G11C2211/5634

摘要： A non-volatile semiconductor memory device includes: an array of electrically rewritable nonvolatile data storage memory cells each having a transistor structure with a control gate; reference current source circuit configured to generate a first reference current adaptable for use during an ordinary read operation and a second reference current for use during a verify-read operation for data status verification in one of writing and erasing events; a sense amplifier configured to compare read currents of a selected memory cell as selected during the ordinary read operation and the verify-read operation with the first and second reference currents respectively to thereby perform data detection; and a driver configured to give an identical voltage to the control gate of the selected memory cell presently selected during the ordinary read operation and the verify-read operation.

摘要翻译： 非挥发性半导体存储器件包括：每个具有带控制栅极的晶体管结构的电可重写非易失性数据存储单元的阵列; 参考电流源电路，被配置为生成适于在普通读取操作期间使用的第一参考电流和用于在写入和擦除事件之一中的数据状态验证的验证读取操作期间使用的第二参考电流; 读出放大器，被配置为将普通读取操作期间所选择的所选存储单元的读取电流与验证读取操作分别与第一和第二参考电流进行比较，从而执行数据检测; 以及驱动器，被配置为向在普通读取操作和验证读取操作期间当前选择的所选择的存储器单元的控制栅极提供相同的电压。

公开(公告)号：US07071771B2

公开(公告)日：2006-07-04

申请号：US10954271

申请日：2004-10-01

申请人： Yoshinori Takano ,  Tadayuki Taura ,  Toru Tanzawa

发明人： Yoshinori Takano ,  Tadayuki Taura ,  Toru Tanzawa

IPC分类号： G05F1/10

CPC分类号： G11C16/3472 ,  G11C11/5621 ,  G11C11/5642 ,  G11C16/28 ,  G11C16/3436 ,  G11C16/3481 ,  G11C2211/5634

摘要： A current difference divider circuit with a plurality of current sources is provided. The divider circuit includes a first current source which is operable to generate a first current, a second current source for generation of a second current less in magnitude than the first current, and a third current source for generating a difference current with its magnitude equivalent to a difference between the first and second currents and for generating a third current resulting from the division thereof. The circuit further includes a fourth current source for generating a fourth current obtainable by mirroring of the second current. The third and fourth currents are added together to provide a fifth current, which is then output.

摘要翻译： 提供了具有多个电流源的电流差分电路。 分频器电路包括第一电流源，其可操作以产生第一电流，第二电流源，用于产生比第一电流更小幅度的第二电流;以及第三电流源，用于产生其电流等于 第一和第二电流之间的差异并且用于产生由其分割产生的第三电流。 电路还包括用于产生可通过镜像第二电流而获得的第四电流的第四电流源。 将第三和第四电流加在一起以提供第五电流，然后输出。

公开(公告)号：US06671203B2

公开(公告)日：2003-12-30

申请号：US10233133

申请日：2002-08-30

申请人： Toru Tanzawa ,  Shigeru Atsumi ,  Akira Umezawa ,  Tadayuki Taura ,  Hitoshi Shiga ,  Yoshinori Takano

发明人： Toru Tanzawa ,  Shigeru Atsumi ,  Akira Umezawa ,  Tadayuki Taura ,  Hitoshi Shiga ,  Yoshinori Takano

IPC分类号： G11C1604

CPC分类号： G11C16/0408 ,  G11C16/08 ,  G11C16/26 ,  G11C29/70

摘要： A nonvolatile semiconductor memory includes first and second nonvolatile memory banks, a data-line for read, a data-line for program and verify, a sense amplifier for read, a sense amplifier for program and verify, and a program circuit. The data-lines are arranged in a region between the first and second nonvolatile memory banks, and selectively connected to the bit-lines of the first and second nonvolatile memory banks. The sense amplifier for read is connected to the data-line for read. The sense amplifier for program and verify and the program circuit are connected to the data-line for program and verify.

摘要翻译： 非易失性半导体存储器包括第一和第二非易失性存储器组，用于读取的数据线，用于编程和验证的数据线，用于读取的读出放大器，用于编程和验证的读出放大器以及程序电路。 数据线布置在第一和第二非易失性存储体之间的区域中，并且选择性地连接到第一和第二非易失性存储体的位线。 用于读取的读出放大器连接到数据线进行读取。 用于程序和验证的读出放大器和程序电路连接到数据线进行程序和验证。

公开(公告)号：US20050117381A1

公开(公告)日：2005-06-02

申请号：US10954271

申请日：2004-10-01

申请人： Yoshinori Takano ,  Tadayuki Taura ,  Toru Tanzawa

发明人： Yoshinori Takano ,  Tadayuki Taura ,  Toru Tanzawa

IPC分类号： G11C11/56 ,  G11C16/28 ,  G11C16/34 ,  G11C11/22

CPC分类号： G11C16/3472 ,  G11C11/5621 ,  G11C11/5642 ,  G11C16/28 ,  G11C16/3436 ,  G11C16/3481 ,  G11C2211/5634

摘要： A current difference divider circuit with a plurality of current sources is provided. The divider circuit includes a first current source which is operable to generate a first current, a second current source for generation of a second current less in magnitude than the first current, and a third current source for generating a difference current with its magnitude equivalent to a difference between the first and second currents and for generating a third current resulting from the division thereof. The circuit further includes a fourth current source for generating a fourth current obtainable by mirroring of the second current. The third and fourth currents are added together to provide a fifth current, which is then output.

摘要翻译： 提供了具有多个电流源的电流差分电路。 分频器电路包括第一电流源，其可操作以产生第一电流，第二电流源，用于产生比第一电流更小幅度的第二电流;以及第三电流源，用于产生其电流等于 第一和第二电流之间的差异并且用于产生由其分割产生的第三电流。 电路还包括用于产生可通过镜像第二电流而获得的第四电流的第四电流源。 将第三和第四电流加在一起以提供第五电流，然后输出。

公开(公告)号：US06795352B2

公开(公告)日：2004-09-21

申请号：US10703005

申请日：2003-11-05

申请人： Toru Tanzawa ,  Shigeru Atsumi ,  Akira Umezawa ,  Tadayuki Taura ,  Hitoshi Shiga ,  Yoshinori Takano

发明人： Toru Tanzawa ,  Shigeru Atsumi ,  Akira Umezawa ,  Tadayuki Taura ,  Hitoshi Shiga ,  Yoshinori Takano

IPC分类号： G11C1604

CPC分类号： G11C16/0408 ,  G11C16/08 ,  G11C16/26 ,  G11C29/70

摘要： The semiconductor memory comprises a reference current generator, first and second current converters, sense amplifiers for read, and sense amplifiers for verify. The reference current generator generates a first voltage dependent upon the current flowing through a reference cell. The first current converters, to which the first voltage is input, each generate a second voltage. The second current converters, to which the first voltage is input, each generate a third voltage. The sense amplifiers for read output data of a selection memory cell, comparing the voltage of the data-line for read with the second voltage. The sense amplifiers for verify output verify data of the selection memory cell, comparing the voltage of the data-lines for verify and the third voltage.

摘要翻译： 半导体存储器包括参考电流发生器，第一和第二电流转换器，用于读出的读出放大器和用于验证的读出放大器。 参考电流发生器根据流过参考单元的电流产生第一电压。 输入第一电压的第一电流转换器各自产生第二电压。 第一电压输入的第二电流转换器各自产生第三电压。 读出放大器，用于选择存储器单元的读取输出数据，将用于读取的数据线的电压与第二电压进行比较。 用于验证输出的读出放大器验证选择存储单元的数据，比较用于验证的数据线的电压和第三电压。

公开(公告)号：US06639837B2

公开(公告)日：2003-10-28

申请号：US10006395

申请日：2001-12-10

申请人： Yoshinori Takano ,  Tadayuki Taura ,  Toru Tanzawa

发明人： Yoshinori Takano ,  Tadayuki Taura ,  Toru Tanzawa

IPC分类号： G11C1606

CPC分类号： G11C16/3472 ,  G11C11/5621 ,  G11C11/5642 ,  G11C16/28 ,  G11C16/3436 ,  G11C16/3481 ,  G11C2211/5621 ,  G11C2211/5634

摘要： A non-volatile semiconductor memory device includes: an array of electrically rewritable nonvolatile data storage memory cells each having a transistor structure with a control gate; reference current source circuit configured to generate a first reference current adaptable for use during an ordinary read operation and a second reference current for use during a verify-read operation for data status verification in one of writing and erasing events; a sense amplifier configured to compare read currents of a selected memory cell as selected during the ordinary read operation and the verify-read operation with the first and second reference currents respectively to thereby perform data detection; and a driver configured to give an identical voltage to the control gate of the selected memory cell presently selected during the ordinary read operation and the verify-read operation.

公开(公告)号：US06999365B2

公开(公告)日：2006-02-14

申请号：US10896701

申请日：2004-07-22

申请人： Yoshinori Takano ,  Shigeru Atsumi ,  Toru Tanzawa

发明人： Yoshinori Takano ,  Shigeru Atsumi ,  Toru Tanzawa

IPC分类号： G11C7/02

CPC分类号： G11C7/062 ,  G11C7/067 ,  G11C7/14 ,  G11C16/28

摘要： A semiconductor memory device is provided using a sense amp circuitry capable of lowering a supply voltage. The semiconductor memory device includes an array of memory cells each configured to store data in accordance with the presence/absence or the magnitude of a current; a sense amp configured to compare a voltage caused on a sense line based on data in a memory cell selected from the array of memory cells with a reference voltage applied to a reference sense line to determine the data; and a reference voltage generator configured to generate the reference voltage applied to the reference sense line.

摘要翻译： 使用能够降低电源电压的读出放大器电路来提供半导体存储器件。 半导体存储器件包括存储单元阵列，每个存储器单元被配置为根据电流的存在/不存在或大小来存储数据; 感测放大器，被配置为基于从存储器单元阵列中选择的存储器单元中的数据与施加到参考感测线的参考电压比较在感测线上引起的电压以确定数据; 以及参考电压发生器，被配置为产生施加到参考感测线的参考电压。

公开(公告)号：US06788601B2

公开(公告)日：2004-09-07

申请号：US10305785

申请日：2002-11-26

申请人： Yoshinori Takano ,  Shigeru Atsumi ,  Toru Tanzawa

发明人： Yoshinori Takano ,  Shigeru Atsumi ,  Toru Tanzawa

IPC分类号： G11C702

CPC分类号： G11C7/062 ,  G11C7/067 ,  G11C7/14 ,  G11C16/28

摘要： A semiconductor memory device comprises memory cell array, a sense amp, and a reference voltage generator. The reference voltage generator includes a reference cell unit containing a reference cell to flow a reference current and a first current source load to supply a current to the reference cell; a reference transistor unit containing a reference transistor to flow a current reflecting the reference current and a second current source load to supply a current to the reference transistor; a control amp for negative feedback control of the reference transistor; a current source transistor; and a third current source load connected to a reference sense line.

摘要翻译： 一种半导体存储器件包括存储单元阵列，一个读出放大器，和一个基准电压generator.The参考电压发生器包括含有参考单元中流动的基准电流和第一电流源负载提供电流的基准的基准电池单元 细胞; 含有参考晶体管的参考晶体管单元中流动反射基准电流和供给电流的参考晶体管的第二电流源负载的电流; 用于参考晶体管的负反馈控制的控制放大器; 电流源晶体管; 以及连接到参考感测线的第三电流源负载。

公开(公告)号：US06552936B2

公开(公告)日：2003-04-22

申请号：US10052303

申请日：2002-01-18

申请人： Hitoshi Shiga ,  Yoshinori Takano ,  Toru Tanzawa ,  Shigeru Atsumi

发明人： Hitoshi Shiga ,  Yoshinori Takano ,  Toru Tanzawa ,  Shigeru Atsumi

IPC分类号： G11C1604

CPC分类号： G11C7/1021 ,  G11C8/10

摘要： There is disclosed a semiconductor integrated circuit device comprising a memory cell array, row decoder, sense amplifier, column gate with two or more stages connected in series, column gate driving circuit, data latch, multiplexer, and address control circuit, and the multiplexer sequentially selects data corresponding to a predetermined address from a plurality of data latched by the data latch. The address control circuit reverses a driving signal for driving at least one stage of the column gate with two or more stages connected in series and selects the columns designated by the next selected plurality of addresses, while the multiplexer sequentially selects the data corresponding to the predetermined address.