公开(公告)号：US5014312A

公开(公告)日：1991-05-07

申请号：US297079

申请日：1989-01-13

Applicant: Gilles Lisimaque ,  Yvon Bahout

Inventor： Gilles Lisimaque ,  Yvon Bahout

IPC: G06F12/14 ,  G06F21/02 ,  G06F21/24 ,  G06K17/00 ,  G06K19/073 ,  G06Q20/34 ,  G06Q20/36 ,  G06Q20/38 ,  G07F7/10

CPC classification number: G07F7/1008 ,  G06Q20/3558 ,  G06Q20/3672 ,  G06Q20/3829

Abstract: The use of chip cards, with the level of security of the type associated with chip cards of the type used by banks, is extended to move widespread use by organizing a secure dispatch of blank chip cards to customers wishing to program specific applications therein. The system consists in sending this customer the blank chip card itself and a programming access key to this card, by separate routes. To prevent any additional risks, the access key is itself enciphered and can be deciphered only be a deciphering element in the possession of the customer. The card can then be programmed only if this card is confronted with its deciphering key.

Abstract translation: 使用具有与银行使用的类型的芯片卡相关联类型的安全级别的芯片卡被扩展以通过组织对希望在其中编程特定应用的客户的安全调度的空白芯片卡来进行广泛使用。 该系统包括通过单独的路由将该客户的空芯片卡本身和编程访问密钥发送到该卡。 为了防止任何额外的风险，访问密钥本身被加密，并且可以被解密，只能是客户拥有的解密元素。 只有当此卡面对其解密密钥时，才能对该卡进行编程。

公开(公告)号：US08717820B2

公开(公告)日：2014-05-06

申请号：US13599222

申请日：2012-08-30

Applicant: Francois Tailliet ,  Yvon Bahout

Inventor： Francois Tailliet ,  Yvon Bahout

IPC: G11C16/04 ,  G11C8/00

CPC classification number: G11C7/1018 ,  G11C8/12

Abstract: A method for electrically programming a non-volatile memory in which a programming cycle includes prior addressing of memory cells from an initial address corresponding to a first row and a column of a memory plane. The method may include addressing the memory cells in a second consecutive row when the end of the first row is reached to store data on bits with consecutive and increasing addresses in two consecutive rows.

Abstract translation: 一种用于电气编程非易失性存储器的方法，其中编程周期包括对应于存储器平面的第一行和列的初始地址的存储器单元的先前寻址。 该方法可以包括在达到第一行的末尾时寻址第二连续行中的存储器单元，以在两个连续行中具有连续和增加的地址的位上存储数据。

公开(公告)号：US06928530B2

公开(公告)日：2005-08-09

申请号：US10081740

申请日：2002-02-22

Applicant: Yvon Bahout

Inventor： Yvon Bahout

IPC: G11C11/413 ,  G06F12/02 ,  G11C8/04 ,  G11C11/41 ,  G06F9/42

CPC classification number: G11C8/04

Abstract: A memory implementing an incremental address counter is sequentially read. An address jump includes detecting an address jump signal, incrementing the incremental address counter, and reading the content of the memory at the incremented address. The content read at the incremented address is transferred into the incremental address counter, and the content of the memory is read at the address contained in the incremental address counter.

Abstract translation: 依次读取实现增量地址计数器的存储器。 地址跳转包括检测地址跳转信号，递增增量地址计数器以及以递增的地址读取存储器的内容。 在增量地址读取的内容被传送到增量地址计数器，并且在包含在增量地址计数器中的地址读取存储器的内容。

公开(公告)号：US5812802A

公开(公告)日：1998-09-22

申请号：US786348

申请日：1997-01-23

Applicant: Yvon Bahout ,  Fran.cedilla.ois Tailliet

Inventor： Yvon Bahout ,  Fran.cedilla.ois Tailliet

IPC: G06F3/00 ,  G06F1/22 ,  G06F13/40 ,  G06F13/00

CPC classification number: G06F1/22 ,  G06F13/4072

Abstract: In order to reduce the number of lines of a standard bus while, at the same time, preserving the compatibility of the communications protocol, the system uses a modified bus. The modification consists in eliminating two power supply lines and in creating a line assigned to a functional signal that is complementary to one of the functional signals of the system. The supply potentials are regenerated from the functional signal and the complementary signal. The disclosed system can be applied notably to systems using I2C buses such as systems using chip-card readers.

公开(公告)号：US5594793A

公开(公告)日：1997-01-14

申请号：US329975

申请日：1994-10-27

Applicant: Yvon Bahout

Inventor： Yvon Bahout

IPC: G06F12/14 ,  G06F21/00 ,  G06F21/24 ,  G11C16/02 ,  G11C16/22 ,  G11C17/00

CPC classification number: G06F21/79 ,  G06F12/1466 ,  G11C16/22

Abstract: To provide efficient protection, in reading mode, of the stored data elements, the integrated circuit has an EEPROM type memory and a lock (L) protecting the zone of the memory. The memory contains a read-protected password (PW) and the circuit has means to release the lock (L) if the circuit receives a write command at the address of the password of the same encrypted password (PW). Application notably to electronic systems and instruments using confidential codes, such as car radios.

Abstract translation: 为了在读取模式下提供存储的数据元素的有效保护，集成电路具有EEPROM型存储器和保护存储器区域的锁（L）。 存储器包含读保护密码（PW），并且如果电路在相同加密密码（PW）的密码地址处接收到写命令，则电路具有释放锁（L）的装置。 尤其适用于使用机密码的电子系统和仪器，如汽车收音机。

公开(公告)号：US08892798B2

公开(公告)日：2014-11-18

申请号：US13253376

申请日：2011-10-05

Applicant: François Tailliet ,  Yvon Bahout

Inventor： François Tailliet ,  Yvon Bahout

IPC: G06F13/00 ,  G06F13/42

CPC classification number: G06F13/4291

Abstract: A method of communication between a master circuit and two slave circuits over a serial bus wherein: the two slave circuits simultaneously transmit their associated identifiers; the two slave circuits simultaneously transmit the inverse of these identifiers; and each slave circuit exploits the combinations present on the bus to determine an order of communication between the two circuits.

Abstract translation: 一种通过串行总线在主电路和两个从属电路之间通信的方法，其中：两个从电路同时发送其相关联的标识符; 两个从电路同时发送这些标识符的逆; 并且每个从电路利用总线上存在的组合来确定两个电路之间的通信顺序。

公开(公告)号：US20130051153A1

公开(公告)日：2013-02-28

申请号：US13599222

申请日：2012-08-30

Applicant: Francois Tailliet ,  Yvon Bahout

Inventor： Francois Tailliet ,  Yvon Bahout

IPC: G11C16/04

CPC classification number: G11C7/1018 ,  G11C8/12

Abstract: A method for electrically programming a non-volatile memory in which a programming cycle includes prior addressing of memory cells from an initial address corresponding to a first row and a column of a memory plane. The method may include addressing the memory cells in a second consecutive row when the end of the first row i is reached to store data on bits with consecutive and increasing addresses in two consecutive rows.

Abstract translation: 一种用于电气编程非易失性存储器的方法，其中编程周期包括对应于存储器平面的第一行和列的初始地址的存储器单元的先前寻址。 该方法可以包括在达到第一行i的末端时在第二个连续行中寻址存储单元，以将数据存储在具有连续和增加地址的位在两个连续的行中。

公开(公告)号：US20120079151A1

公开(公告)日：2012-03-29

申请号：US13253376

申请日：2011-10-05

Applicant: François Tailliet ,  Yvon Bahout

Inventor： François Tailliet ,  Yvon Bahout

IPC: G06F13/00

CPC classification number: G06F13/4291

Abstract: A method of communication between a master circuit and two slave circuits over a serial bus wherein: the two slave circuits simultaneously transmit their associated identifiers; the two slave circuits simultaneously transmit the inverse of these identifiers; and each slave circuit exploits the combinations present on the bus to determine an order of communication between the two circuits.

Abstract translation: 一种通过串行总线在主电路和两个从属电路之间通信的方法，其中：两个从电路同时发送其相关联的标识符; 两个从电路同时发送这些标识符的逆; 并且每个从电路利用总线上存在的组合来确定两个电路之间的通信顺序。

公开(公告)号：US06523121B1

公开(公告)日：2003-02-18

申请号：US08259967

申请日：1994-06-14

Applicant: Yvon Bahout ,  François Tailliet

Inventor： Yvon Bahout ,  François Tailliet

IPC: G06F1300

CPC classification number: G06F1/22 ,  G06F13/4072

Abstract: In order to reduce the number of lines of a standard bus while, at the same time, preserving the compatibility of the communications protocol, the system uses a modified bus. The modification consists in eliminating two power supply lines and in creating a line assigned to a functional signal that is complementary to one of the functional signals of the system. The supply potentials are regenerated from the functional signal and the complementary signal. The disclosed system can be applied notably to systems using I2C buses such as systems using chip-card readers.

Abstract translation: 为了减少标准总线的数量，同时保持通信协议的兼容性，系统使用修改的总线。 该修改包括消除两条电源线，并创建一条分配给功能信号的线路，该功能信号与该系统的一个功能信号互补。 电源电位从功能信号和互补信号再生。 所公开的系统可以特别地应用于使用I2C总线的系统，例如使用芯片卡读取器的系统。

公开(公告)号：US5742548A

公开(公告)日：1998-04-21

申请号：US340940

申请日：1994-11-17

Applicant: Yvon Bahout ,  Fran.cedilla.ois Tailliet

Inventor： Yvon Bahout ,  Fran.cedilla.ois Tailliet

IPC: G11C17/00 ,  G11C16/02 ,  G11C16/04 ,  G11C29/00 ,  G11C29/04 ,  G11C29/24 ,  G11C29/52 ,  G11C7/00

CPC classification number: G11C29/52 ,  G11C29/24

Abstract: In order to make it possible to ascertain that the programming cycles in an EEPROM type memory have been carried out efficiently, supplementary test cells are provided. A data writing operation is carried out in three successive cycles that consist in the programming of a test cell with a first logic value, a second cycle for the programming of the data elements and a third cycle for the programming of the test cell with a logic value that is complementary to the first one. The state of the test cell enables the detection of power interruptions during programming.

Abstract translation: 为了能够确定EEPROM型存储器中的编程周期已经被有效地执行，提供了补充测试单元。 数据写入操作在三个连续周期中进行，其中包括具有第一逻辑值的测试单元的编程，用于编程数据元件的第二周期，以及具有逻辑的测试单元编程的第三周期 价值与第一个互补。 测试单元的状态使得能够在编程期间检测电源中断。