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公开(公告)号：US12093176B2
公开(公告)日：2024-09-17
申请号：US18341088
申请日：2023-06-26
IPC分类号： G06F12/0891 , G06F12/0804 , G11C5/02 , G11C5/04 , G11C7/22
CPC分类号： G06F12/0804 , G06F12/0891 , G11C5/025 , G11C5/04 , G11C7/22 , G06F2212/1008 , G06F2212/1032 , G06F2212/45 , G06F2212/608 , H01L2224/16225 , H01L2924/15311
摘要： A memory system includes multiple groups of primary memory cells residing in a first die or a stack of first dies, multiple groups of cache memory cells residing in a second die, an interposer, and control circuits residing in a third die. Each group of the cache memory cells is associated with a corresponding group of the primary memory cells. The first die or the stack of first dies is coupled to a top surface of the second die through a first group of bumps. A bottom surface of the second die is coupled to a top surface of the interposer through a second group of bumps. The control circuits are associated with the primary memory cells and the cache memory cells. The third die is positioned aside the second die and coupled to the top surface of the interposer through a third group of pumps.
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公开(公告)号：US20240103898A1
公开(公告)日：2024-03-28
申请号：US17954886
申请日：2022-09-28
申请人： Dell Products L.P.
发明人： Doron Tal , Adnan Sahin
IPC分类号： G06F9/455 , G06F12/0875
CPC分类号： G06F9/45558 , G06F12/0875 , G06F2009/45579 , G06F2009/45583 , G06F2212/45
摘要： An apparatus comprises a processing device configured to receive, from one of two or more storage nodes of a software-defined storage system comprising a write cache and persistent storage, a request to read a given portion of data. One or more portions of data in the persistent storage are also stored as read-only data in local storage of virtual computing instances implementing the storage nodes. The processing device is configured to read the given portion of data from the local storage of the virtual computing instances responsive to determining that the given portion of data is part of the read-only data in the local storage of the virtual computing instances, and to read the given portion of data from the write cache or persistent storage responsive to determining that the given portion of data is not part of the read-only data in the local storage of the virtual computing instances.
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公开(公告)号：US20240028519A1
公开(公告)日：2024-01-25
申请号：US18106559
申请日：2023-02-07
申请人： Dell Products L.P.
发明人： Weibing Zhang , Lei Gao , Donglei Wang , Shuning Zhang , Jianping Song
IPC分类号： G06F12/0875
CPC分类号： G06F12/0875 , G06F2212/45
摘要： Techniques for data processing involve: performing, according to a determination that a programmable circuit receives user-written data, data feature detection by the programmable circuit on a first part of the user-written data. Such techniques further involve: replacing, in response to the first part matching a predetermined data feature, the first part by the programmable circuit with a data representation corresponding to the predetermined data feature. In addition, such techniques involve: writing the data representation to a cache region of a storage system. Accordingly, such techniques can save cache resources of a storage system and can save CPU of the storage system, thus avoiding the latency due to data feature detection and improving the user experience.
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公开(公告)号：US20240004555A1
公开(公告)日：2024-01-04
申请号：US18176446
申请日：2023-02-28
申请人： Kioxia Corporation
发明人： Kazuhiro FUKUTOMI
IPC分类号： G06F3/06 , G06F12/0802
CPC分类号： G06F3/0616 , G06F3/0653 , G06F3/0679 , G06F12/0802 , G06F2212/304 , G06F2212/45
摘要： A memory system includes a nonvolatile memory that includes a plurality of regions; a volatile memory; and a controller that is connected to the nonvolatile memory and the volatile memory. The controller is configured to store in the volatile memory a plurality of first counter values each indicating the number of times each of the plurality of regions has been accessed and a plurality of second counter values respectively corresponding to the plurality of first counter values, and write the first counter value of a first region of the plurality of regions to the nonvolatile memory in response to the second counter value of the first region being equal to or more than a threshold value.
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公开(公告)号：US20230333981A1
公开(公告)日：2023-10-19
申请号：US18341088
申请日：2023-06-26
IPC分类号： G06F12/0804 , G11C5/04 , G11C5/02 , G06F12/0891 , G11C7/22
CPC分类号： G06F12/0804 , G11C5/04 , G11C5/025 , G06F12/0891 , G11C7/22 , H01L2224/16225 , H01L2924/15311 , G06F2212/1008 , G06F2212/1032 , G06F2212/45 , G06F2212/608
摘要： A memory system includes multiple groups of primary memory cells residing in a first die or a stack of first dies, multiple groups of cache memory cells residing in a second die, an interposer, and control circuits residing in a third die. Each group of the cache memory cells is associated with a corresponding group of the primary memory cells. The first die or the stack of first dies is coupled to a top surface of the second die through a first group of bumps. A bottom surface of the second die is coupled to a top surface of the interposer through a second group of bumps. The control circuits are associated with the primary memory cells and the cache memory cells. The third die is positioned aside the second die and coupled to the top surface of the interposer through a third group of pumps.
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公开(公告)号：US11755497B2
公开(公告)日：2023-09-12
申请号：US17197425
申请日：2021-03-10
申请人： Arm Limited
IPC分类号： G06F12/1027
CPC分类号： G06F12/1027 , G06F2212/45
摘要： Memory management apparatus comprises input circuitry to receive a translation request defining a first memory address within a first memory address space; prediction circuitry to generate a predicted second memory address within a second memory address space as a predicted translation of the first memory address, the predicted second memory address being a predetermined function of the first memory address; control circuitry to initiate processing of the predicted second memory address; translation and permission circuitry to perform an operation to generate a translated second memory address for the first memory address associated with permission information to indicate whether memory access is permitted to the translated second memory address; and output circuitry to provide the translated second memory address as a response to the translation request when the permission information indicates that access is permitted to the translated second memory address.
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公开(公告)号：US20230273871A1
公开(公告)日：2023-08-31
申请号：US18111423
申请日：2023-02-17
发明人： Markus Sven Grönlund
IPC分类号： G06F11/36 , G06F12/0875
CPC分类号： G06F11/3636 , G06F12/0875 , G06F2212/45
摘要： Techniques for incremental stack walking are disclosed, including: performing a stack walk of a runtime stack, at least by traversing the runtime stack from a current frame to a root frame, to obtain a set of stack walking results; storing a cache of the set of stack walking results; and installing, on the runtime stack, a marker frame that marks a boundary of stack frames represented by the set of stack walking results.
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公开(公告)号：US20190258579A1
公开(公告)日：2019-08-22
申请号：US15898407
申请日：2018-02-16
发明人： Omar CAREY , Rajsekhar DAS
IPC分类号： G06F12/0873 , G06F12/0817 , G06F12/0808 , G06F9/38
CPC分类号： G06F12/0238 , G06F2212/1016 , G06F2212/45 , G06F2212/7207
摘要： A cluster allocation bitmap determines which clusters in a band of storage remain unallocated. However, concurrent access to a cluster allocation bitmap can cause CPU stalls as copies of the cluster allocation bitmap in a CPU's level 1 (L1) cache are invalidated by another CPU allocating from the same bitmap. In one embodiment, cluster allocation bitmaps are divided into L1 cache line sized and aligned chunks. Each core of a multicore CPU is directed at random to allocate space out of a chunk. Because the chunks are L1 cache line aligned, the odds of the same portion of the cluster allocation bitmap being loaded into multiple L1 caches by multiple CPU cores is reduced, reducing the odds of an L1 cache invalidation. The number of CPU cores performing allocations on a given cluster allocation bitmap is limited based on the number of chunks with unallocated space that remain.
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公开(公告)号：US10067944B2
公开(公告)日：2018-09-04
申请号：US15402119
申请日：2017-01-09
申请人： Splunk, Inc.
IPC分类号： G06F12/00 , G06F17/30 , G06F12/0873 , G06F12/0868 , G06F12/0866 , G06F12/0802 , G06F12/0871 , G06F12/0862 , G06F3/06
CPC分类号： G06F12/0875 , G06F16/172 , G06F16/951 , G06F16/9574 , G06F2212/1021 , G06F2212/45 , G06F2212/6024 , G06F2212/6026 , G06F2212/6028
摘要： Embodiments are disclosed for performing cache aware searching. In response to a search query, a first bucket and a second bucket in remote storage for processing the search query. A determination is made that a first file in the first bucket is present in a cache when the search query is received. In response to the search query, a search is performed using the first file based on the determination that the first file is present in the cache when the search query is received, and the search is performed using a second file from the second bucket once the second file is stored in the cache.
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公开(公告)号：US20180210664A1
公开(公告)日：2018-07-26
申请号：US15415966
申请日：2017-01-26
申请人： Reduxio Systems Ltd.
发明人： Uri WEISSBREM
IPC分类号： G06F3/06 , G06F12/0875
CPC分类号： G06F3/0619 , G06F3/0653 , G06F3/0656 , G06F3/0673 , G06F12/0875 , G06F2212/1032 , G06F2212/154 , G06F2212/263 , G06F2212/45
摘要： A system and method for managing a storage system may include recording, in a cache memory, data related to user writes to the storage system; setting a time in a next consistency point (NCP) object with a value greater than the current time; and maintaining a first counter related to the number of user writes recorded in the cache memory and that occurred before the time included in the NCP object and after a time included in a consistency point (CP) object; maintaining a second counter related to the number of user writes that were stored in a persistent storage system and that occurred before the time in the NCP object and after a time in the CP object. A system and method for managing a storage system may include initializing the storage system to a consistent state based on the time included in the CP object.
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