公开(公告)号：US08619882B2

公开(公告)日：2013-12-31

申请号：US12330279

申请日：2008-12-08

申请人： Uichi Sekimoto

发明人： Uichi Sekimoto

IPC分类号： H04B14/06

CPC分类号： H03M7/3026 ,  H03M7/3031

摘要： A data modulation circuit has an adder adding an input signal, and an output signal of a memory device; and an output circuit part discriminating and quantizing the output signal of the adder by a predetermined threshold value. The memory device receives and holds the output signal of the adder and a predetermined signal, and supplies the held signals to the adder as an output signal of the memory device.

摘要翻译： 数据调制电路具有添加输入信号的加法器和存储器件的输出信号; 以及输出电路部分，将加法器的输出信号鉴别和量化预定阈值。 存储器件接收并保持加法器的输出信号和预定信号，并将保持的信号作为存储器件的输出信号提供给加法器。

公开(公告)号：US07289050B1

公开(公告)日：2007-10-30

申请号：US11477139

申请日：2006-06-27

申请人： Rajiv Laroia ,  Tom Richardson ,  Frank A. Lane

发明人： Rajiv Laroia ,  Tom Richardson ,  Frank A. Lane

IPC分类号： H03M3/00

CPC分类号： H03M7/3006 ,  H03M3/386 ,  H03M3/50 ,  H03M7/3017 ,  H03M7/3028 ,  H03M7/3031 ,  H03M7/304

摘要： Methods and apparatus for implementing and/or using amplifiers and performing various amplification related operations are described. The methods are well suited for use with, but not limited to, switching type amplifiers. The methods and apparatus described herein allow for the use of switching amplifiers while reducing and/or compensating for distortions that the use of such amplifiers would normally create. The described methods and apparatus can be used alone or in combination with various novel signaling schemes which can make it easier to compensate for the non-ideal behavior of switching amplifiers in such a way as to enable practical application in wireless transmission and/or other applications.

摘要翻译： 描述了用于实现和/或使用放大器并执行各种放大相关操作的方法和装置。 这些方法非常适用于但不限于开关型放大器。 本文描述的方法和装置允许使用开关放大器，同时减少和/或补偿通常使用这种放大器的失真。 所描述的方法和装置可以单独使用或与各种新颖的信令方案组合使用，这可以使得更容易以这样的方式补偿开关放大器的非理想行为，使得无线传输和/或其他应用中的实际应用 。

公开(公告)号：US20050030093A1

公开(公告)日：2005-02-10

申请号：US10921016

申请日：2004-08-18

申请人： Erlend Olson ,  Ion Opris

发明人： Erlend Olson ,  Ion Opris

IPC分类号： H03F3/217 ,  H03M3/02 ,  H03M7/32 ,  H03F3/38

CPC分类号： H03M7/3006 ,  H03F3/2173 ,  H03F2200/331 ,  H03M3/43 ,  H03M3/496 ,  H03M7/3031

摘要： A system and method of creating a highly efficient digital amplifier which can take either analog or digital inputs, and produce a high power accurate representation of the input to drive speakers or other low impedance load is described. The system employs a transition detector and delay unit which allows the comparator of the signal modulator to ignore its inputs for a pre-determined number of subsequent clock cycles once an output transition has been detected. Through the use of faster clocks and variable clock cycle skips upon the comparator's output transition, finer resolution of the feedback's clock period for noise-shaping purposes is achieved. Finer resolution of the clock period allows the present invention to employ a more aggressive noise-shaping than previously possible. In another aspect of the invention; additional delta-sigma modulator noise suppression is obtained by using the common bridge implementation of the power output stage with the improvement of configuring the bridge to create a 3-state condition instead of the conventional 2 states. By controlling the two halves of the bridge independently of one another, an output with 3 states makes for improved noise shaping performance.

摘要翻译： 描述了一种创建高效数字放大​​器的系统和方法，该数字放大器可以采用模拟或数字输入，并且产生用于驱动扬声器或其他低阻抗负载的输入的高功率精确表示。 一旦检测到输出转换，该系统采用转换检测器和延迟单元，其允许信号调制器的比较器忽略其输入以用于预定数量的后续时钟周期。 通过使用更快的时钟和可变时钟周期跳过比较器的输出转换，实现了用于噪声整形的反馈时钟周期的更好的分辨率。 时钟周期的更好的分辨率允许本发明采用比先前可能的更积极的噪声整形。 在本发明的另一方面; 通过使用功率输出级的公共桥接实现，通过改进配置桥以创建3态条件而不是传统的2状态来获得额外的Δ-Σ调制器噪声抑制。 通过彼此独立地控制桥的两半，具有3个状态的输出改善了噪声整形性能。

公开(公告)号：US4652858A

公开(公告)日：1987-03-24

申请号：US852749

申请日：1986-04-16

申请人： Masaru Kokubo ,  Shigeo Nishita ,  Kazuo Yamakido

发明人： Masaru Kokubo ,  Shigeo Nishita ,  Kazuo Yamakido

IPC分类号： H03M1/08 ,  H03M1/00 ,  H03M3/02 ,  H03M1/66

CPC分类号： H03M7/3031 ,  H03M3/50 ,  H03M7/3026

摘要： An oversampling type digital-to-analog converter which has a light gradient overload and a high signal-to-noise ratio in spite of a comparatively low sampling frequency.In a digital-to-analog converter wherein the difference between an oversampled digital input signal and a feedback signal is taken, such differences are integrated, the integral value is quantized to obtain the feedback signal, and part of the feedback signal is used as an analog output signal; a circuit for the quantization is constructed of a circuit which converts the integral value into a digital signal smaller in the number of bits than the digital input signal, and the feedback signal is obtained by integrating the outputs of the quantization circuit by means of a digital integral circuit.

摘要翻译： 尽管采样频率相对较低，但过采样型数模转换器具有光梯度过载和高信噪比。 在采用过采样数字输入信号和反馈信号之间的差分的数模转换器中，积分这样的差值，对积分值进行量化以获得反馈信号，反馈信号的一部分被用作 模拟输出信号; 用于量化的电路由将积分值转换成数字信号比数字输入信号更小的数字信号的电路构成，反馈信号是通过将数字量化电路 积分电路。

公开(公告)号：US07773017B1

公开(公告)日：2010-08-10

申请号：US12283841

申请日：2008-09-16

申请人： Runsheng He ,  Haoli Qian

发明人： Runsheng He ,  Haoli Qian

IPC分类号： H03M3/00

CPC分类号： H03M7/3031 ,  H03M7/3026 ,  H03M7/3042

摘要： A noise shaping module includes a first addition module that receives an N-bit digital input signal, where N is an integer greater than one. A first filter module generates a first filtered output signal based on an output signal of the first addition module. A truncation module generates an M-bit truncated output signal based on the first filtered output signal, where M is an integer less than N. A second filter module generates a second filtered output signal based on the M-bit truncated output signal. The second filtered output signal is an input to the first addition module.

摘要翻译： 噪声整形模块包括第一加法模块，其接收N位数字输入信号，其中N是大于1的整数。 第一滤波器模块基于第一加法模块的输出信号产生第一滤波输出信号。 截断模块基于第一滤波输出信号产生M位截断的输出信号，其中M是小于N的整数。第二滤波器模块基于M位截断输出信号产生第二滤波输出信号。 第二滤波输出信号是第一加法模块的输入。

公开(公告)号：US07425910B1

公开(公告)日：2008-09-16

申请号：US11526485

申请日：2006-09-25

申请人： Runsheng He ,  Haoli Qian

发明人： Runsheng He ,  Haoli Qian

IPC分类号： H03M3/00

CPC分类号： H03M7/3031 ,  H03M7/3026 ,  H03M7/3042

摘要： A noise shaping circuit and method for operating the same includes a first addition module that receives a digital input signal. A first filter module generates a first filtered output signal based on an output of the first addition module. A truncation module generates a truncated output signal based on first filtered output signal. A second filter module generates a second filtered output signal based on the truncated output signal. The second filtered output signal is an input to the first addition module.

摘要翻译： 噪声整形电路及其操作方法包括接收数字输入信号的第一加法模块。 第一滤波器模块基于第一加法模块的输出产生第一滤波输出信号。 截断模块基于第一滤波输出信号产生截断的输出信号。 第二滤波器模块基于截断的输出信号产生第二滤波输出信号。 第二滤波输出信号是第一加法模块的输入。

公开(公告)号：US07230556B2

公开(公告)日：2007-06-12

申请号：US11197252

申请日：2005-08-04

申请人： Jochen Rivoir

发明人： Jochen Rivoir

IPC分类号： H03M3/00

CPC分类号： H03M7/3013 ,  H03M3/344 ,  H03M3/50 ,  H03M7/3024 ,  H03M7/3031

摘要： A method for generating an analog signal based on samples representing the analog signal includes feeding the samples into a delta-sigma modulator, the delta-sigma modulator outputting a sequence of bits, and introducing a non-linear time-discrete function into a feedback loop between a quantizer element and a delta element of the delta-sigma modulator, where arguments of the non-linear time-discrete function include a current bit and at least one bit previous to the current bit.

摘要翻译： 基于表示模拟信号的样本产生模拟信号的方法包括将样本馈送到Δ-Σ调制器中，Δ-Σ调制器输出比特序列，并将非线性时间离散函数引入反馈回路 在Δ-Σ调制器的量化器元件和delta元件之间，其中非线性时间离散函数的参数包括当前位和当前位之前的至少一个位。

公开(公告)号：US20050078023A1

公开(公告)日：2005-04-14

申请号：US10948654

申请日：2004-09-24

申请人： Tetsuya Matsumoto

发明人： Tetsuya Matsumoto

IPC分类号： H03M1/66 ,  H03M1/68 ,  H03M3/02 ,  H03M3/04 ,  H03M7/36 ,  H03M3/00

CPC分类号： H03M3/344 ,  H03M3/358 ,  H03M3/502 ,  H03M7/3026 ,  H03M7/3031

摘要： An analog signal outputting circuit comprises two unit analog circuits for outputting an analog signal, corresponding to levels “−1” or “1”, and a low-pass filter for smoothing the analog signal output from the two unit analog circuits, as selected by codes output from the four-valued delta-sigma modulator. In case the input signal is −2 or +2, outputs of the unit analog circuits are summed together to output an analog signal corresponding to −2 or +2. In case the input signal is −1 or +1, outputs of the unit analog circuits are alternately used to output an analog signal corresponding to −1 or +1 to reduce the non-linearity error resulting from variations in the analog devices.

摘要翻译： 模拟信号输出电路包括两个单元模拟电路，用于输出对应于电平“-1”或“1”的模拟信号，以及低通滤波器，用于平滑从两个单元模拟电路输出的模拟信号，如由 从四值Δ-Σ调制器输出的代码。 在输入信号为-2或+2的情况下，将单位模拟电路的输出相加在一起，输出对应于-2或+2的模拟信号。 在输入信号为-1或+1的情况下，单位模拟电路的输出交替用于输出对应于-1或+1的模拟信号，以减少由模拟装置的变化引起的非线性误差。

公开(公告)号：US06842131B1

公开(公告)日：2005-01-11

申请号：US10847399

申请日：2004-05-18

申请人： Li-Sheng Lo ,  Tung-Tsai Liao

发明人： Li-Sheng Lo ,  Tung-Tsai Liao

IPC分类号： H03M7/32 ,  H03M7/36 ,  H03M3/00

CPC分类号： H03M7/3015 ,  H03M7/3026 ,  H03M7/3031

摘要： A Delta-Sigma modulator is disclosed, which has a Delta adder, a Sigma adder, a first latch, a second latch and a feedback generator, wherein the feedback generator provides a feedback signal to the Delta adder based on a pre-stage data signal provided by the first latch, so that the Delta adder provides a pre-stage addition signal. The Sigma adder performs an accumulation to provide an accumulative signal to the first latch, so that the first latch provides a pre-stage data signal to the second latch to enable the second latch to output a digital output signal.

摘要翻译： 公开了一种Δ-Σ调制器，其具有Δ加法器，Sigma加法器，第一锁存器，第二锁存器和反馈发生器，其中反馈发生器基于前级数据信号向Delta加法器提供反馈信号 由第一锁存器提供，使得Δ加法器提供前级加法信号。 Sigma加法器执行累加以向第一锁存器提供累加信号，使得第一锁存器向第二锁存器提供前级数据信号，以使第二锁存器能够输出数字输出信号。

公开(公告)号：US06765518B2

公开(公告)日：2004-07-20

申请号：US10214239

申请日：2002-08-07

申请人： Erlend Olson ,  Ion Opris

发明人： Erlend Olson ,  Ion Opris

IPC分类号： H03M300

CPC分类号： H03M7/3006 ,  H03F3/2173 ,  H03F2200/331 ,  H03M3/43 ,  H03M3/496 ,  H03M7/3031

摘要： A system and method of creating a highly efficient digital amplifier which can take either analog or digital inputs, and produce a high power accurate representation of the input to drive speakers or other low impedance load is described. The system employs a transition detector and delay unit which allows the comparator of the signal modulator to ignore its inputs for a pre-determined number of subsequent clock cycles once an output transition has been detected. Through the use of faster clocks and variable clock cycle skips upon the comparator's output transition, finer resolution of the feedback's clock period for noise-shaping purposes is achieved. Finer resolution of the clock period allows the present invention to employ a more aggressive noise-shaping than previously possible. In another aspect of the invention, additional delta-sigma modulator noise suppression is obtained by using the common bridge implementation of the power output stage with the improvement of configuring the bridge to create a 3-state condition instead of the conventional 2 states. By controlling the two halves of the bridge independently of one another, an output with 3 states makes for improved noise shaping performance.

摘要翻译： 描述了一种创建高效数字放大​​器的系统和方法，该数字放大器可以采用模拟或数字输入，并且产生用于驱动扬声器或其他低阻抗负载的输入的高功率精确表示。 一旦检测到输出转换，该系统采用转换检测器和延迟单元，其允许信号调制器的比较器忽略其输入以用于预定数量的后续时钟周期。 通过使用更快的时钟和可变时钟周期跳过比较器的输出转换，实现了用于噪声整形的反馈时钟周期的更好的分辨率。 时钟周期的更好的分辨率允许本发明采用比先前可能的更积极的噪声整形。在本发明的另一方面，通过使用功率输出级的公共桥接实现来获得附加的Δ-Σ调制器噪声抑制， 改进配置桥以创建3状态而不是传统的2状态。 通过彼此独立地控制桥的两半，具有3个状态的输出改善了噪声整形性能。