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公开(公告)号：US4652858A
公开(公告)日：1987-03-24
申请号：US852749
申请日：1986-04-16
申请人： Masaru Kokubo , Shigeo Nishita , Kazuo Yamakido
发明人： Masaru Kokubo , Shigeo Nishita , Kazuo Yamakido
CPC分类号： H03M7/3031 , H03M3/50 , H03M7/3026
摘要： An oversampling type digital-to-analog converter which has a light gradient overload and a high signal-to-noise ratio in spite of a comparatively low sampling frequency.In a digital-to-analog converter wherein the difference between an oversampled digital input signal and a feedback signal is taken, such differences are integrated, the integral value is quantized to obtain the feedback signal, and part of the feedback signal is used as an analog output signal; a circuit for the quantization is constructed of a circuit which converts the integral value into a digital signal smaller in the number of bits than the digital input signal, and the feedback signal is obtained by integrating the outputs of the quantization circuit by means of a digital integral circuit.
摘要翻译： 尽管采样频率相对较低，但过采样型数模转换器具有光梯度过载和高信噪比。 在采用过采样数字输入信号和反馈信号之间的差分的数模转换器中，积分这样的差值，对积分值进行量化以获得反馈信号，反馈信号的一部分被用作 模拟输出信号; 用于量化的电路由将积分值转换成数字信号比数字输入信号更小的数字信号的电路构成，反馈信号是通过将数字量化电路 积分电路。
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2.发明授权
公开(公告)号：US4796296A
公开(公告)日：1989-01-03
申请号：US739295
申请日：1985-05-30
申请人： Eiichi Amada , Kazuo Yamakido , Takahiko Kozaki , Shigeo Nishita , Masaru Kokubo
发明人： Eiichi Amada , Kazuo Yamakido , Takahiko Kozaki , Shigeo Nishita , Masaru Kokubo
摘要： A CODEC including a coder and decoder to construct the subscriber's circuit of a digital telephone switching system or the like, wherein an analogue balancing circuit is provided between the output terminal of a post-filter and the input terminal of a pre-filter in order to effectively eliminate a return signal in the case of two-wire/four-wire conversion, and return signals not eliminated by the analogue balancing circuit are further eliminated by a digital balancing circuit.Especially in the present invention, the analogue balancing circuit is so constructed that its characteristics are independent of frequencies, and hence, the analogue balancing circuit and the digital balancing circuit are readily implemented as an LSI.
摘要翻译： 包括编码器和解码器的编解码器构成数字电话交换系统等的用户电路，其中模拟平衡电路设置在后置滤波器的输出端和预滤波器的输入端之间，以便 在双线/四线转换的情况下有效地消除了返回信号，并且数字平衡电路进一步消除了模拟平衡电路未消除的返回信号。 特别是在本发明中，模拟平衡电路被构造为使其特性与频率无关，因此模拟平衡电路和数字平衡电路容易实现为LSI。
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公开(公告)号：US4787080A
公开(公告)日：1988-11-22
申请号：US894861
申请日：1986-08-08
摘要： A PCM coder and decoder circuit for use in a subscriber line interface circuit of a telephone communication system has a digital balancing network for removing any echo signal. The digital balancing network is formed by series-connecting a first balancing circuit having characteristics corresponding to the fixed characteristics of a coder, decoder, etc. and a second balancing circuit having characteristics corresponding to variable characteristics of an external circuit including two-wire transmission line which is connected to the coder and decoder circuit. Thus, a replica of an echo signal is precisely produced, and the circuit configuration is simplified.
摘要翻译： 用于电话通信系统的用户线接口电路中的PCM编码器和解码器电路具有用于去除任何回波信号的数字平衡网络。 数字平衡网络通过串联连接具有与编码器，解码器等的固定特性相对应的特性的第一平衡电路和具有对应于包括双线传输线的外部电路的可变特性的特性的第二平衡电路 其连接到编码器和解码器电路。 因此，精确地产生回波信号的复制品，并且简化了电路配置。
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公开(公告)号：US4591827A
公开(公告)日：1986-05-27
申请号：US702224
申请日：1985-02-15
申请人： Shigeo Nishita , Kazuo Yamakido , Kenichi Ohwada
发明人： Shigeo Nishita , Kazuo Yamakido , Kenichi Ohwada
摘要： Disclosed is a PCM coder-decoder having a construction such that a digital filter contained originally in the PCM coder-decoder is utilized on the time division basis in order to fold back a digital reception signal to a digital signal transmission side and thus to accomplish interruption, communication exchange between three parties, gain control, fold-over test of the PCM signal, and so forth, in addition to the coding and decoding functions inherent to the PCM coder-decoder.
摘要翻译： 公开了一种PCM编码器解码器，其结构使得最初在PCM编码器 - 解码器中包含的数字滤波器在时间分割的基础上被使用，以便将数字接收信号折回到数字信号发送侧，从而完成中断 ，三方之间的通信交换，增益控制，PCM信号的折叠测试等等，以及PCM编码器 - 解码器固有的编码和解码功能。
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公开(公告)号：US4672361A
公开(公告)日：1987-06-09
申请号：US769310
申请日：1985-08-26
申请人： Masaru Kokubo , Shigeo Nishida , Kazuo Yamakido
发明人： Masaru Kokubo , Shigeo Nishida , Kazuo Yamakido
摘要： Disclosed is an interpolative A/D converter for converting an over-sampled analog signal into a digital signal without the occurrence of over slope distortions, wherein the difference between the analog input signal and an analog feedback signal derived from the converter output through D/A conversion is integrated, the integrated output is compared with several reference voltages and, after being converted into a digital signal, the comparison result is integrated in a digital manner to complete a digital output signal of the A/D converter.
摘要翻译： 公开了一种用于将过采样的模拟信号转换为数字信号而不发生过度斜率失真的内插A / D转换器，其中模拟输入信号与通过D / A输出的转换器得到的模拟反馈信号之间的差异 转换集成，将集成输出与几个参考电压进行比较，在转换成数字信号后，以数字方式集成比较结果，完成A / D转换器的数字输出信号。
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公开(公告)号：US4366439A
公开(公告)日：1982-12-28
申请号：US185805
申请日：1980-09-10
申请人： Kazuo Yamakido
发明人： Kazuo Yamakido
CPC分类号： H04B14/048 , H03M1/68
摘要： A PCM decoder for converting to an analog voice signal an 8-bit PCM signal the first bit of which is a polarity specifying bit, the PCM decoder comprising a capacitor array having binary-weighted capacitors and a resistor string circuit having plural resistors for dividing a reference voltage to obtain different tap voltages, wherein the tap voltages corresponding to the four lower bits of the PCM signal are derived from the resistor string circuit and the combination of the reference voltage and each of the tap voltages, made according to the contents of the second, third and fourth bits of the PCM signal is applied to the corresponding one of the capacitors in the capacitor array circuit whereby the capacitor array circuit delivers an analog voltage signal corresponding to the received signal, the resistor string circuit having two groups of intermediate taps so that the conversion characteristic for obtaining voltages in the signalling frame may be different from that in the non-signalling frame.
摘要翻译： 一种用于将模拟语音信号转换为第一位为极性指定位的8位PCM信号的PCM解码器，PCM解码器包括具有二进制加权电容器的电容器阵列和具有多个电阻器的电阻器串电路， 参考电压以获得不同的抽头电压，其中对应于PCM信号的四个较低位的抽头电压从电阻器串电路导出，并且参考电压和每个抽头电压的组合根据 PCM信号的第二，第三和第四位被施加到电容器阵列电路中的对应的一个电容器中，由此电容器阵列电路传递与接收信号对应的模拟电压信号，电阻器串电路具有两组中间抽头 使得用于获得信令帧中的电压的转换特性可以不同于非信号帧中的电压的转换特性 吊架
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7.发明授权Phase demodulator receiving inputs from phase detector and binary phase detector 失效相位解调器从相位检测器和二进制相位检测器接收输入
公开(公告)号：US5406218A
公开(公告)日：1995-04-11
申请号：US194074
申请日：1994-02-09
IPC分类号： H03D3/20 , H04L27/233
CPC分类号： H04L27/2332 , H03D3/20 , H03D2200/0039 , H03D2200/005
摘要： A demodulation circuit comprises: a phase detection circuit for determining an absolute value of a phase difference between an input signal to be demodulated and a reference signal; a binary phase detection circuit for converting a phase lead or lag between the input signal and the reference signal into a sign of phase difference; and a phase demodulation circuit for calculating, from the absolute value and the sign of phase difference, a phase difference quantity between the input signal and the reference signal and for performing a delay detection on the phase difference quantity; wherein the binary phase detection circuit includes a delay circuit which generates a delay time corresponding to the operation delay of the phase detection circuit; and wherein the phase detection circuit includes a level limiter circuit to limit an internal signal voltage and a reference voltage adjust circuit to correct deviations in the internal signal voltage.
摘要翻译： 解调电路包括：相位检测电路，用于确定要解调的输入信号和参考信号之间的相位差的绝对值; 二进制相位检测电路，用于将输入信号和参考信号之间的相位超前或滞后转换为相位差的符号; 以及相位解调电路，用于从相位差的绝对值和符号计算输入信号和参考信号之间的相位差量，并对相位差量进行延迟检测; 其中二进制相位检测电路包括产生与相位检测电路的运算延迟相对应的延迟时间的延迟电路; 并且其中所述相位检测电路包括限制内部信号电压的电平限制器电路和参考电压调整电路以校正所述内部信号电压的偏差。
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8.发明授权Over-sampling analog-to-digital converter using a current switching circuit as a local digital-to-analog converter 失效使用电流开关电路作为本地数模转换器的过采样模数转换器
公开(公告)号：US5227795A
公开(公告)日：1993-07-13
申请号：US704599
申请日：1991-05-23
摘要： An over-sampling analog-to-digital converter using a current switching circuit 102 as a local digital-to-analog converter, wherein a difference between the output currents Isig and Iq of a voltage-to-current converter circuit 101 and a current switching circuit is integrated by a capacitor 105 of which the one end is grounded to a dc potential VB. Further, the current switching circuit 102 has many bits to decrease the difference current between the signal current Isig and the feedback current signal Iq. Moreover, the level-shifting function of the voltage-to-current converter circuit 101 makes it possible to apparently subtract the dc component from the input analog signal Vsig which is produced based on an internally generated dc voltage as a dc bias voltage, and to decrease a change in the voltage between the electrodes of a capacitor caused by the integration of current.
摘要翻译： 使用电流开关电路102作为本地数模转换器的过采样模数转换器，其中电压 - 电流转换器电路101的输出电流Isig和Iq之间的差异以及电流切换 电路通过其一端接地到直流电位VB的电容器105来集成。 此外，电流开关电路102具有许多位以减小信号电流Isig和反馈电流信号Iq之间的差电流。 此外，电压 - 电流转换器电路101的电平转换功能使得可以从基于内部产生的直流电压产生的输入模拟信号Vsig显然地减去直流分量作为直流偏置电压，并且 降低由电流的积分引起的电容器电极之间的电压变化。
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公开(公告)号：US4945359A
公开(公告)日：1990-07-31
申请号：US326743
申请日：1989-03-21
申请人： Kazuo Yamakido
发明人： Kazuo Yamakido
IPC分类号： H03M3/02
CPC分类号： H03M3/418
摘要： Herein disclosed is an oversampling type A/D converter, wherein there are connected in multiple stages units interpolation type A/D conversion circuits each including: an analog integration circuit for integrating the difference between an analog input signal and a feedback signal; a voltage comparison circuit for adding the integrated signal and said difference to produce a digital signal on the basis of the added value; a digital integration circuit for integrating the digital signal coming from the voltage comparison circuit; a feedback load D/A conversion circuit for producing a feedback signal from the output of the digital integration circuit; and an addition circuit for adding the output and input of said digital integration circuit.
摘要翻译： 这里公开了一种过采样型A / D转换器，其中多级单元连接插值型A / D转换电路，每个包括：模拟积分电路，用于对模拟输入信号和反馈信号之间的差进行积分; 电压比较电路，用于根据所述相加值添加所述积分信号和所述差值以产生数字信号; 用于对来自电压比较电路的数字信号进行积分的数字积分电路; 用于从数字积分电路的输出产生反馈信号的反馈负载D / A转换电路; 以及用于将所述数字积分电路的输出和输入相加的加法电路。
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公开(公告)号：US4250492A
公开(公告)日：1981-02-10
申请号：US840178
申请日：1977-10-07
申请人： Kazuo Yamakido , Nobuo Tsukamoto
发明人： Kazuo Yamakido , Nobuo Tsukamoto
CPC分类号： H03M1/0863 , H03M1/40 , H03M1/74
摘要： A non-uniform weighting circuitry which is effective for enhancing speed and accuracy in the operations of encoders and decoders comprises in a cascade connection a constant current switch, a variable attenuator, a polarity changing circuit and a uniform weighting circuit. An impedance converting means is provided to make at least one of input and output terminals of the variable attenuator to be of low impedance, whereby spike-like noises generated by a switching element constituting a part of the variable attenuator is reduced.
摘要翻译： 对于增强编码器和解码器的运算速度和精度有效的非均匀加权电路包括恒定电流开关，可变衰减器，极性改变电路和均匀加权电路的级联。 提供阻抗转换装置，使可变衰减器的输入和输出端中的至少一个具有低阻抗，由此构成可变衰减器的一部分的开关元件产生的尖峰状噪声减小。
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