公开(公告)号：US20100295585A1

公开(公告)日：2010-11-25

申请号：US12851597

申请日：2010-08-06

申请人： KAZUO YAMAKIDO ,  Takashi Nakamura

发明人： KAZUO YAMAKIDO ,  Takashi Nakamura

IPC分类号： H03L7/06

CPC分类号： H03L7/0995 ,  H03L7/085 ,  H03L7/093 ,  H03L2207/50

摘要： The semiconductor integrated circuit includes a clock generating section having a digital control signal generating part operable to generate a clock signal and a digital control part. The clock generating section further includes a phase-frequency comparator and a control register. The comparator is supplied with a reference signal CLKin and a feedback signal. The control register is supplied with an output signal of the comparator, and stores two or larger bits of digital control information. The clock generating section further includes a control data storing circuit for previously storing sets of initial set data for lock operations. In response to operation select information, initial set data are stored at upper bit of the control register from the control data storing circuit. Thus, it becomes possible to reduce the number of steps to store control information in a register for digitally controlling the clock signal generating part.

摘要翻译： 半导体集成电路包括具有可操作以产生时钟信号的数字控制信号产生部分和数字控制部分的时钟产生部分。 时钟产生部分还包括相位频率比较器和控制寄存器。 比较器被提供有参考信号CLKin和反馈信号。 控制寄存器提供比较器的输出信号，并存储两个或更多位的数字控制信息。 时钟产生部分还包括用于预先存储用于锁定操作的初始设置数据集合的控制数据存储电路。 响应于操作选择信息，初始设定数据被存储在来自控制数据存储电路的控制寄存器的高位。 因此，可以减少将控制信息存储在用于数字控制时钟信号产生部分的寄存器中的步骤数。

公开(公告)号：US4366439A

公开(公告)日：1982-12-28

申请号：US185805

申请日：1980-09-10

申请人： Kazuo Yamakido

发明人： Kazuo Yamakido

IPC分类号： H03M1/66 ,  H03M1/00 ,  H04B14/04 ,  H03K9/00

CPC分类号： H04B14/048 ,  H03M1/68

摘要： A PCM decoder for converting to an analog voice signal an 8-bit PCM signal the first bit of which is a polarity specifying bit, the PCM decoder comprising a capacitor array having binary-weighted capacitors and a resistor string circuit having plural resistors for dividing a reference voltage to obtain different tap voltages, wherein the tap voltages corresponding to the four lower bits of the PCM signal are derived from the resistor string circuit and the combination of the reference voltage and each of the tap voltages, made according to the contents of the second, third and fourth bits of the PCM signal is applied to the corresponding one of the capacitors in the capacitor array circuit whereby the capacitor array circuit delivers an analog voltage signal corresponding to the received signal, the resistor string circuit having two groups of intermediate taps so that the conversion characteristic for obtaining voltages in the signalling frame may be different from that in the non-signalling frame.

摘要翻译： 一种用于将模拟语音信号转换为第一位为极性指定位的8位PCM信号的PCM解码器，PCM解码器包括具有二进制加权电容器的电容器阵列和具有多个电阻器的电阻器串电路， 参考电压以获得不同的抽头电压，其中对应于PCM信号的四个较低位的抽头电压从电阻器串电路导出，并且参考电压和每个抽头电压的组合根据 PCM信号的第二，第三和第四位被施加到电容器阵列电路中的对应的一个电容器中，由此电容器阵列电路传递与接收信号对应的模拟电压信号，电阻器串电路具有两组中间抽头 使得用于获得信令帧中的电压的转换特性可以不同于非信号帧中的电压的转换特性 吊架

公开(公告)号：US06963298B2

公开(公告)日：2005-11-08

申请号：US10152638

申请日：2002-05-23

申请人： Masanori Otsuka ,  Kazuo Yamakido ,  Etsuji Yamamoto ,  Shinya Sano

发明人： Masanori Otsuka ,  Kazuo Yamakido ,  Etsuji Yamamoto ,  Shinya Sano

IPC分类号： H03M1/36 ,  H03M1/12

CPC分类号： H03M1/363

摘要： An AD converter which uses no buffer for receiving the input signals or uses the buffer having relaxed requirements concerning the range of input signals and the output impedance. Voltage at the connection points of a resistor ladder in which a plurality of resistor elements are connected in series, are compared with a reference voltage by a plurality of voltage comparators, a first current circuit is provided on the high potential side of the resistor ladder, a second current circuit is provided on the low potential side thereof, and analog input voltages are fed by providing an input terminal at any place of the resistor ladder except both ends thereof.

摘要翻译： AD转换器，其不使用缓冲器来接收输入信号，或者使用具有放宽的关于输入信号的范围和输出阻抗的要求的缓冲器。 将多个电阻元件串联连接的电阻梯的连接点的电压与多个电压比较器与参考电压进行比较，在电阻梯的高电位侧设置第一电流电路， 在其低电位侧提供第二电流电路，并且通过在除电阻梯的两端的任何位置设置输入端子来馈送模拟输入电压。

公开(公告)号：US5392456A

公开(公告)日：1995-02-21

申请号：US592340

申请日：1990-10-03

申请人： Isamu Mitomo ,  Nobuo Tsukamoto ,  Arata Nakagoshi ,  Jiroh Sakaguchi ,  Kazuo Yamakido ,  Hiroshi Noguchi ,  Atushi Hoshi

发明人： Isamu Mitomo ,  Nobuo Tsukamoto ,  Arata Nakagoshi ,  Jiroh Sakaguchi ,  Kazuo Yamakido ,  Hiroshi Noguchi ,  Atushi Hoshi

IPC分类号： H03H11/04 ,  H03H11/12 ,  H04B7/26 ,  H04B1/10

CPC分类号： H03H11/1291

摘要： A method of controlling the time constant of a filter for use in a radio receiver which receives a signal, transmitted from a transmitting station at a predetermined period, intermittently at the predetermined period and demodulates and delivers the received signal, a filter circuit having the time constant control function based on the method, and a radio receiver having the filter circuit. Preferably, the filter has its time constant switchable stepwise and specifically, parallel connection of capacitors or shortcircuiting of resistors is controlled by turning on/off switches. A controller within the filter circuit or the radio receiver performs control for applying a predetermined periodical signal (or standard pulse signal) to the filter and controlling the time constant of the filter in accordance with an output signal (or triangular pulse) during a first time zone within each operation interval for the intermittent reception and for filtering the signal from the transmitting station and causing a demodulating circuit to demodulate and deliver a filtered signal.

摘要翻译： 一种控制无线电接收机中使用的滤波器的时间常数的方法，该无线电接收机接收以预定周期从发送站以预定周期间歇地发送的信号，并且对接收到的信号进行解调和传送，具有时间 基于该方法的恒定控制功能和具有滤波器电路的无线电接收机。 优选地，该滤波器的时间常数可逐步切换，具体地说，通过接通/断开开关来控制电容器的并联或电阻的短路。 滤波器电路或无线电接收机内的控制器执行用于将预定周期信号（或标准脉冲信号）施加到滤波器的控制，并且在第一时间内根据输出信号（或三角波脉冲）控制滤波器的时间常数 在间歇接收的每个操作间隔内，对来自发送站的信号进行滤波，并使解调电路解调并传送滤波信号。

公开(公告)号：US5157398A

公开(公告)日：1992-10-20

申请号：US778246

申请日：1991-10-17

申请人： Takao Okazaki ,  Kazuo Yamakido

发明人： Takao Okazaki ,  Kazuo Yamakido

IPC分类号： H03M1/12 ,  H03M1/38 ,  H03M1/44

CPC分类号： H03M1/44

摘要： In an A/D convertor, one comparator is provided for the most significant bit of the output digital signal, two for the second bit, and three each for the third and lower-order bits. When a compare operation is being performed by one of the three comparators that are provided for each of the third and lower bits, the remaining two comparators provide outputs in response to which output switch circuits perform setting of two reference voltages that are specified by the comparison result of a comparator corresponding to an output digital signal two bits higher.

摘要翻译： 在A / D转换器中，为输出数字信号的最高有效位提供一个比较器，对于第二位提供两个比较器，对于第三位和低位位提供三个比较器。 当为三位和低位中的每一位提供三个比较器中的一个比较器进行比较操作时，剩下的两个比较器提供输出，响应哪个输出开关电路执行由比较指定的两个参考电压的设置 比较器对应于两位高的输出数字信号的结果。

公开(公告)号：US4652858A

公开(公告)日：1987-03-24

申请号：US852749

申请日：1986-04-16

申请人： Masaru Kokubo ,  Shigeo Nishita ,  Kazuo Yamakido

发明人： Masaru Kokubo ,  Shigeo Nishita ,  Kazuo Yamakido

IPC分类号： H03M1/08 ,  H03M1/00 ,  H03M3/02 ,  H03M1/66

CPC分类号： H03M7/3031 ,  H03M3/50 ,  H03M7/3026

摘要： An oversampling type digital-to-analog converter which has a light gradient overload and a high signal-to-noise ratio in spite of a comparatively low sampling frequency.In a digital-to-analog converter wherein the difference between an oversampled digital input signal and a feedback signal is taken, such differences are integrated, the integral value is quantized to obtain the feedback signal, and part of the feedback signal is used as an analog output signal; a circuit for the quantization is constructed of a circuit which converts the integral value into a digital signal smaller in the number of bits than the digital input signal, and the feedback signal is obtained by integrating the outputs of the quantization circuit by means of a digital integral circuit.

摘要翻译： 尽管采样频率相对较低，但过采样型数模转换器具有光梯度过载和高信噪比。 在采用过采样数字输入信号和反馈信号之间的差分的数模转换器中，积分这样的差值，对积分值进行量化以获得反馈信号，反馈信号的一部分被用作 模拟输出信号; 用于量化的电路由将积分值转换成数字信号比数字输入信号更小的数字信号的电路构成，反馈信号是通过将数字量化电路 积分电路。

公开(公告)号：USRE32313E

公开(公告)日：1986-12-23

申请号：US692197

申请日：1985-01-17

申请人： Kazuo Yamakido

发明人： Kazuo Yamakido

IPC分类号： H03M1/00

CPC分类号： H03M1/58

摘要： A PCM encoder for converting a voice signal into a eight-bit code by approximating the .mu.-low characteristic where .mu.=255 with 15 segments comprises a capacitor array circuit including eight capacitors for determining lowermost voltages of the segments, a resistor string circuit for producing step voltage in each of the segments, a comparator circuit for comparing the output voltage of the capacitor array circuit with a reference voltage, and a successive approximation register circuit for controlling switch groups provided in the capacitor array circuit and the resistor string circuit. The resistor string circuit is provided with taps for deriving voltages corresponding to (2n-1)/33 (where n=1-16) of a voltage applied across the resistor string. A PCM encoder which conforms to the .mu.-low with high fidelity and is capable of quantizing mid-tread at the first segment is disclosed.

公开(公告)号：US20090195277A1

公开(公告)日：2009-08-06

申请号：US12365743

申请日：2009-02-04

申请人： Kazuo YAMAKIDO ,  Takashi Nakamura

发明人： Kazuo YAMAKIDO ,  Takashi Nakamura

IPC分类号： H03L7/06

CPC分类号： H03L7/0995 ,  H03L7/085 ,  H03L7/093 ,  H03L2207/50

摘要： The semiconductor integrated circuit includes a clock generating section having a digital control signal generating part operable to generate a clock signal and a digital control part. The clock generating section further includes a phase-frequency comparator and a control register. The comparator is supplied with a reference signal CLKin and a feedback signal. The control register is supplied with an output signal of the comparator, and stores two or larger bits of digital control information. The clock generating section further includes a control data storing circuit for previously storing sets of initial set data for lock operations. In response to operation select information, initial set data are stored at upper bit of the control register from the control data storing circuit. Thus, it becomes possible to reduce the number of steps to store control information in a register for digitally controlling the clock signal generating part.

摘要翻译： 半导体集成电路包括具有可操作以产生时钟信号的数字控制信号产生部分和数字控制部分的时钟产生部分。 时钟产生部分还包括相位频率比较器和控制寄存器。 比较器被提供有参考信号CLKin和反馈信号。 控制寄存器提供比较器的输出信号，并存储两个或更多位的数字控制信息。 时钟产生部分还包括控制数据存储电路，用于预先存储用于锁定操作的初始设置数据集。 响应于操作选择信息，初始设定数据被存储在来自控制数据存储电路的控制寄存器的高位。 因此，可以减少将控制信息存储在用于数字控制时钟信号产生部分的寄存器中的步骤数。

公开(公告)号：US5406218A

公开(公告)日：1995-04-11

申请号：US194074

申请日：1994-02-09

申请人： Yukihito Ishihara ,  Kazuo Yamakido ,  Takao Okazaki ,  Katsuhiro Furukawa

发明人： Yukihito Ishihara ,  Kazuo Yamakido ,  Takao Okazaki ,  Katsuhiro Furukawa

IPC分类号： H03D3/20 ,  H04L27/233

CPC分类号： H04L27/2332 ,  H03D3/20 ,  H03D2200/0039 ,  H03D2200/005

摘要： A demodulation circuit comprises: a phase detection circuit for determining an absolute value of a phase difference between an input signal to be demodulated and a reference signal; a binary phase detection circuit for converting a phase lead or lag between the input signal and the reference signal into a sign of phase difference; and a phase demodulation circuit for calculating, from the absolute value and the sign of phase difference, a phase difference quantity between the input signal and the reference signal and for performing a delay detection on the phase difference quantity; wherein the binary phase detection circuit includes a delay circuit which generates a delay time corresponding to the operation delay of the phase detection circuit; and wherein the phase detection circuit includes a level limiter circuit to limit an internal signal voltage and a reference voltage adjust circuit to correct deviations in the internal signal voltage.

摘要翻译： 解调电路包括：相位检测电路，用于确定要解调的输入信号和参考信号之间的相位差的绝对值; 二进制相位检测电路，用于将输入信号和参考信号之间的相位超前或滞后转换为相位差的符号; 以及相位解调电路，用于从相位差的绝对值和符号计算输入信号和参考信号之间的相位差量，并对相位差量进行延迟检测; 其中二进制相位检测电路包括产生与相位检测电路的运算延迟相对应的延迟时间的延迟电路; 并且其中所述相位检测电路包括限制内部信号电压的电平限制器电路和参考电压调整电路以校正所述内部信号电压的偏差。

公开(公告)号：US5227795A

公开(公告)日：1993-07-13

申请号：US704599

申请日：1991-05-23

申请人： Kazuo Yamakido ,  Norimitsu Nishikawa ,  Katsuhiro Furukawa ,  Yuko Tamba ,  Takao Okazaki

发明人： Kazuo Yamakido ,  Norimitsu Nishikawa ,  Katsuhiro Furukawa ,  Yuko Tamba ,  Takao Okazaki

IPC分类号： H03M3/04 ,  H03M3/02

CPC分类号： H03M3/434 ,  H03M3/456

摘要： An over-sampling analog-to-digital converter using a current switching circuit 102 as a local digital-to-analog converter, wherein a difference between the output currents Isig and Iq of a voltage-to-current converter circuit 101 and a current switching circuit is integrated by a capacitor 105 of which the one end is grounded to a dc potential VB. Further, the current switching circuit 102 has many bits to decrease the difference current between the signal current Isig and the feedback current signal Iq. Moreover, the level-shifting function of the voltage-to-current converter circuit 101 makes it possible to apparently subtract the dc component from the input analog signal Vsig which is produced based on an internally generated dc voltage as a dc bias voltage, and to decrease a change in the voltage between the electrodes of a capacitor caused by the integration of current.

摘要翻译： 使用电流开关电路102作为本地数模转换器的过采样模数转换器，其中电压 - 电流转换器电路101的输出电流Isig和Iq之间的差异以及电流切换 电路通过其一端接地到直流电位VB的电容器105来集成。 此外，电流开关电路102具有许多位以减小信号电流Isig和反馈电流信号Iq之间的差电流。 此外，电压 - 电流转换器电路101的电平转换功能使得可以从基于内部产生的直流电压产生的输入模拟信号Vsig显然地减去直流分量作为直流偏置电压，并且 降低由电流的积分引起的电容器电极之间的电压变化。