摘要:
The present invention discloses BPSK demodulator, which uses a delay circuit to delay a BPSK signal and mixes the delayed BPSK signal with the undelayed BPSK signal to output a demodulated data signal, and which uses a phase rotation circuit and the demodulated data signal to obtain a carrier clock signal. The operating frequency of the delay circuit is the same as or 0.5 times the carrier frequency. Therefore, the present invention consumes less power and is realized by digital circuits and analog circuits.
摘要:
Cost, electronic circuitry limitations, and communication channel behavior yield communication systems with strict bandwidth constraints. Hence, maximally utilizing available bandwidth is crucial, for example in wireless networks, to supporting ever increasing numbers of users and their demands for increased data volumes, low latency, and high download speeds. Accordingly, it would be beneficial for such networks to support variable bandwidth allocations such that smaller frequency sub-bands are allocated to users, as their number increases, but the individual users/nodes insert more data-carrying signals in order to compensate for the loss of operating bandwidth arising from the accommodation of more users. It would further be beneficial for transmitters and receivers according to embodiments of such a network architecture to be based upon low cost design methodologies allowing their deployment within a wide range of applications including high volume, low cost consumer electronics for example.
摘要:
Provided is a broadband frequency detector, more particularly, to a frequency detector detecting all the signals for guiding the safe vehicle operation, and radar signals for determining vehicle speeds. The broadband frequency detector comprises: a horn antenna configured to receive signals having specific frequencies; a first amplifier configured to receive the signals having specific frequencies from the horn antenna; a mixer unit configured to receive signals from the first amplifier, wherein the signals are low noise amplified therein; and a second amplifier, arranged in parallel with the amplifier, for transferring signals to the mixer unit after low noise amplifying the signal received from the horn antenna, wherein the second amplifier includes a transistor and a first microwave circuit unit for matching the impedance of the horn antenna and the impedance of the transistor.
摘要:
Apparatus and methods disclosed herein perform gain, clipping, and phase compensation in the presence of I/Q mismatch in quadrature RF receivers. Gain and phase mismatch are exacerbated by differences in clipping between I & Q signals in low resolution ADCs. Signals in the stronger channel arm are clipped differentially more than weaker signals in the other channel arm. Embodiments herein perform clipping operations during iterations of gain mismatch calculations in order to balance clipping between the I and Q channel arms. Gain compensation coefficients are iteratively converged, clipping levels are established, and data flowing through the network is gain and clipping compensated. A compensation phase angle and phase compensation coefficients are then determined from gain and clipping compensated sample data. The resulting phase compensation coefficients are applied to the gain and clipping corrected receiver data to yield a gain, clipping, and phase compensated data stream.
摘要:
In a first circuit for detecting clock glitches in a clock signal, a master counter is clocked by the clock signal and memorizes a master count. An incrementer advances the master count by one increment. A slave counter is clocked by the clock signal and memorizes a slave count. The slave count is retarded relative to the master count by at least a particular number of clock edges. A comparator determines whether the difference between the master count and the slave count is at least a value of the incrementer times the particular number of clock edges.
摘要:
The present invention discloses a method and system for adaptively identifying signal bandwidth. The method includes: performing digitizing intermediate frequency processing to the received signal and outputting in-phase/quadrature (I/Q) signals; identifying signal bandwidth of the I/Q signals according to at least two signal identification templates and outputting the synchronized signal flows after a successful identification. A system for adaptively identifying signal bandwidth is also disclosed. The present invention can be compatible with at least two bandwidth modes, and the software can automatically perform identification and switch of the modulation bandwidth, when manual invention is not necessary and the operation is simple.
摘要:
Methods and systems according to one or more embodiments are provided for frequency detection. In an embodiment, a frequency detector is provided that includes a capacitor that discharges or charges responsive to binary states of an input signal.
摘要:
A radio communication apparatus operable over a wide range of frequencies including a signal processing device is provided. The device performs an analog to digital conversion at a predetermined sample rate independent of a selected frequency band within the wide range of frequencies to generate a digital signal, and digitally processes the digital signal to output a data signal at baseband associated with the selected frequency band.
摘要:
There is provided a solution for simultaneous reception of dual channel transmission. The solution is based on applying a first and a second oscillating signals, mixing and adding in order to separate the in-phase and quadrature components of first and second signals from a combined radio frequency signal received as input.
摘要:
A method and an apparatus for calibrating a low frequency clock are disclosed. The method includes: calculating a frequency of a low frequency clock in a current low frequency clock calibration; and calculating an average value of low frequency clock frequencies in n clock calibrations before the current calibration, where n is greater than 1 and is an integer; judging whether a difference between the frequency of the low frequency clock in the current low frequency clock calibration and the average value is smaller than a preset threshold for the difference; and if the difference between the frequency of the low frequency clock in the current low frequency clock calibration and the average value is smaller than the preset threshold for the difference, calculating the number of sleep cycles according to the calculated and obtained frequency of the low frequency clock in the current low frequency clock calibration.