公开(公告)号：US08255599B2

公开(公告)日：2012-08-28

申请号：US11390754

申请日：2006-03-28

申请人： Nadim Shaikli

发明人： Nadim Shaikli

IPC分类号： G06F3/00 ,  G06F13/36

CPC分类号： H04L47/50 ,  G06F13/4022 ,  G06F2213/0026 ,  H04L47/10 ,  H04L47/6215 ,  H04L47/624 ,  H04L47/6275 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9052 ,  H04L49/9057 ,  H04L49/9094

摘要： In PCI-Express and alike communications systems, data bandwidth per channel can vary as a result of negotiated port bifurcation during network bring-up. Disclosed are systems and methods for adjusting FIFO depths in response to negotiated bandwidth per channel so that data absorbing FIFO's of respective channels are not arbitrarily too deep or too shallow relative to the data bandwidths of the channels the FIFO's serve.

摘要翻译： 在PCI-Express和相似的通信系统中，每个通道的数据带宽可能因网络启动过程中协商的端口分岔而变化。 公开了用于响应于每个通道的协商带宽来调整FIFO深度的系统和方法，使得相应信道的数据吸收FIFO相对于FIFO服务的信道的数据带宽不是任意太深或太浅。

公开(公告)号：US08248741B2

公开(公告)日：2012-08-21

申请号：US12561189

申请日：2009-09-16

申请人： Jeffrey G. Barrow

发明人： Jeffrey G. Barrow

IPC分类号： H02H9/00 ,  H02H3/22

CPC分类号： H01L27/0262

摘要： A SCR-based based electrostatic discharge protection device with a shunt path is provided. The shunt path operates at a low resistance when an enabling signal of the shunt path is asserted and a high resistance when the enabling signal is negated. The shunt path connects the cathode and the gate of the silicon-controlled rectifier, and provides a conductive path for displacement current from a parasitic capacitance when the shunt path is enabled, such as when power is provided to the device, and further allows the SCR to enter a low-resistance state when the shunt path is not enabled, such as when power is not provided to the device. A threshold trigger circuit is operably coupled between the anode and the cathode of the silicon-controlled rectifier and is configured to provide a current path when the anode voltage reaches a predetermined value lower than a breakdown voltage of the silicon-controlled rectifier.

摘要翻译： 提供了一种具有分流路径的基于SCR的静电放电保护装置。 当分路路径的使能信号被断言时，并联路径工作在低电阻，当使能信号被否定时，分路路径工作在低电阻。 分流路径连接可控硅整流器的阴极和栅极，并且当分路路径被使能时，例如当向器件供电时，提供用于来自寄生电容的位移电流的导电路径，并且还允许SCR 当并联路径未使能时，例如当未向设备供电时，进入低电阻状态。 阈值触发电路可操作地耦合在可控硅整流器的阳极和阴极之间，并且被配置为当阳极电压达到比硅可控整流器的击穿电压低的预定值时提供电流路径。

公开(公告)号：US08248383B2

公开(公告)日：2012-08-21

申请号：US12427460

申请日：2009-04-21

申请人： Christopher William Dews ,  Charles Henry Seaborg, Jr.

发明人： Christopher William Dews ,  Charles Henry Seaborg, Jr.

IPC分类号： G06F3/041

CPC分类号： G06F3/045 ,  G06F3/044

摘要： A touch screen includes a plurality of single-layer ITO bars having a substantially rectangular shape and arranged in parallel to each other in order to detect touches on the touch screen. The location of a touch on the touch screen in the direction along an ITO bar is determined by applying a signal on one end of the ITO bar and measuring the change in the amplitude and the delay of the signal on the opposite end of the ITO bar. Such application and measurement of the signal can be repeated with the application of the signal occurring on the opposite end of the ITO bar and the measurement of the signal occurring on said one end of the ITO bar, in order to enhance the accuracy of the measurement.

摘要翻译： 触摸屏包括多个单层ITO棒，其具有大致矩形形状并且彼此平行地布置，以便检测触摸屏上的触摸。 通过在ITO棒的一端上施加信号并测量ITO棒的另一端的信号的振幅和延迟的变化来确定触摸屏上沿ITO条的方向上的触摸位置 。 信号的这种应用和测量可以通过施加在ITO棒的相对端上发生的信号和在ITO棒的所述一端上发生的信号的测量来重复，以便提高测量的精度 。

公开(公告)号：US08230174B2

公开(公告)日：2012-07-24

申请号：US11040926

申请日：2005-01-21

申请人： Mario Au ,  Jason Z. Mo ,  Xiaoping Fang

发明人： Mario Au ,  Jason Z. Mo ,  Xiaoping Fang

IPC分类号： G06F12/00 ,  G06F13/00

CPC分类号： G06F5/065

摘要： A multi-queue FIFO memory device that uses existing pins of the device to load a desired number of queues (N) into a queue number register is provided. The queue number register is coupled to a queue size look-up table (LUT), which provides a queue size value in response to the contents of the queue number register. The queue size value indicates the amount of memory (e.g., the number of memory blocks) to be included in each of the N queues. The queue size value is provided to a queue start/end address generator, which automatically generates the start and end address associated with each queue in response to the queue size value. These start and end addresses are stored in queue address register files, which enable proper memory read/write and flag counter operations.

摘要翻译： 提供了使用设备的现有引脚将期望数量的队列（N）加载到队列号寄存器中的多队列FIFO存储器设备。 队列号寄存器被耦合到队列大小查询表（LUT），其响应于队列号寄存器的内容提供队列大小值。 队列大小值指示要包括在每个N个队列中的存储器量（例如，存储器块的数量）。 队列大小值被提供给队列开始/结束地址生成器，其响应于队列大小值自动生成与每个队列相关联的开始和结束地址。 这些开始和结束地址存储在队列地址寄存器文件中，这样可以实现适当的存储器读/写和标志计数器操作。

公开(公告)号：US08217689B2

公开(公告)日：2012-07-10

申请号：US12675106

申请日：2010-01-19

申请人： Lu Yang ,  Sibing Wang ,  Xiaoqian Zhang

发明人： Lu Yang ,  Sibing Wang ,  Xiaoqian Zhang

IPC分类号： H03L7/06

CPC分类号： H03L7/0807 ,  H03L7/16

摘要： A method and a circuit are described for recovery of video clocks for a DisplayPort receiver. The disclosure includes two clock dividers, a direct digital synthesis (DDS), a fixed multiplier Phase-Locked Loop (PLL) on a DisplayPort video system. A DisplayPort receiver link clock is divided to a lower frequency as the input of the DDS which can lower the performance requirement on a DDS circuit. The output from a time stamp value indirectly controls a direct digital synthesis device, which then drives a PLL to generate the recovery clock signal. The technique is suitable for implementation on an integrated circuit and Field Programmable Gate array system.

摘要翻译： 描述了一种用于恢复DisplayPort接收机的视频时钟的方法和电路。 本公开包括两个时钟分频器，直接数字合成（DDS），DisplayPort视频系统上的固定乘法器锁相环（PLL）。 DisplayPort接收器链路时钟被划分为较低频率作为DDS的输入，这可以降低DDS电路的性能要求。 来自时间戳值的输出间接地控制直接数字合成装置，然后驱动PLL以产生恢复时钟信号。 该技术适用于集成电路和现场可编程门阵列系统的实现。

公开(公告)号：US08174969B1

公开(公告)日：2012-05-08

申请号：US12625491

申请日：2009-11-24

申请人： Raghunath Reddy Kommidi ,  David Alan Brown

发明人： Raghunath Reddy Kommidi ,  David Alan Brown

IPC分类号： H04L12/26

CPC分类号： H04L49/50

摘要： A packet switch includes a flow control circuit for preventing a downstream ingress port of the packet switch from providing a non-posted packet to an upstream egress port of the packet switch when a downstream egress port of the packet switch is congested. As a result, congestion is reduced in the downstream egress port. Additionally, congestion is reduced in an upstream ingress port of the packet switch that receives completion packets in response to non-posted packets output from the upstream egress port and provides the completion packets to the downstream egress port. Because congestion is reduced in the upstream ingress port, latency is reduced for a completion packet received at the upstream ingress port and provided to another downstream egress port of the packet switch in response to a non-posted packet provided from another downstream ingress port to the upstream egress port and output from the packet switch.

摘要翻译： 分组交换机包括流控制电路，用于当分组交换机的下游出口端口拥塞时，防止分组交换机的下游进入端口向分组交换机的上游出口端口提供非分支分组。 结果，下游出口端口拥塞减少。 此外，响应于从上游出口端口输出的非发布分组，接收完成分组的分组交换机的上游入口端口的拥塞减少，并向下游出口端口提供完成分组。 由于上游入口端口的拥塞减少，所以在上游入口端口接收到的完成分组的延迟会减少，并且响应于从另一个下游进入端口提供的非发布分组提供给分组交换机的另一个下游出口端口 上行出口端口和分组交换机的输出。

公开(公告)号：US08085070B2

公开(公告)日：2011-12-27

申请号：US12338970

申请日：2008-12-18

申请人： Qichang Wu ,  Shuo Liu ,  Juan Qiao

发明人： Qichang Wu ,  Shuo Liu ,  Juan Qiao

IPC分类号： H03L7/06

CPC分类号： H03L7/1974 ,  G06F1/08

摘要： A novel solution that combines the technologies of fractional divider and phase selection is provided to implement over-clocking for CPU PLL in PC clock generator with a set resolution that is independent of the clock frequency.

摘要翻译： 提供了组合分数分频器和相位选择技术的新颖解决方案，以实现与PC时钟发生器中的CPU PLL的超频，其设置分辨率与时钟频率无关。

公开(公告)号：US07983374B2

公开(公告)日：2011-07-19

申请号：US11904875

申请日：2007-09-28

申请人： Leon Lei ,  Han Bi

发明人： Leon Lei ,  Han Bi

IPC分类号： H04L7/00 ,  H06G1/12

CPC分类号： H04L25/14 ,  H03K5/135 ,  H03M9/00

摘要： A method and apparatus for varying an output clock signal frequency to match the frequency of an output data signal frequency for a SERDES circuit while maintaining a constant input clock frequency is shown. According to this method and apparatus, a PMA rate signal may control the frequency of the output clock while a datastrobe signal may be used to control the frequency of the data signal. Accordingly, the apparatus and methods may be used to produce an output data signal and a clock signal having frequencies that may be lower than the frequency of the input clock signal.

摘要翻译： 示出了用于改变输出时钟信号频率以匹配SERDES电路的输出数据信号频率的频率同时保持恒定的输入时钟频率的方法和装置。 根据该方法和装置，PMA速率信号可以控制输出时钟的频率，同时可以使用数据探测器信号来控制数据信号的频率。 因此，该装置和方法可用于产生具有可能低于输入时钟信号的频率的频率的输出数据信号和时钟信号。

公开(公告)号：US20110170577A1

公开(公告)日：2011-07-14

申请号：US12687821

申请日：2010-01-14

申请人： Kiomars Anvari

发明人： Kiomars Anvari

IPC分类号： H04L5/16 ,  G06F13/38 ,  G06F13/12 ,  H03M1/12 ,  H03M1/66 ,  G06F13/42

CPC分类号： H04L5/16

摘要： A high-speed switch that includes a switch fabric, and both high-speed serial ports and data converter physical ports. A first set of data converter physical ports may perform analog-to-digital conversions, such that an external analog signal may be converted to a digital input signal on the switch. The converted digital input signal may then be routed through the switch fabric in accordance with a serial data protocol. A second set of data converter physical ports may perform digital-to-analog conversions, such that an internal digital signal received from the switch fabric may be converted to an analog output signal on the switch. The converted analog output signal may then be transmitted to an external destination in accordance with a serial data protocol.

摘要翻译： 一种高速交换机，包括交换矩阵，以及高速串行端口和数据转换器物理端口。 第一组数据转换器物理端口可以执行模数转换，使得外部模拟信号可以被转换成开关上的数字输入信号。 转换的数字输入信号然后可以根据串行数据协议通过交换结构路由。 第二组数据转换器物理端口可以执行数模转换，使得从交换结构接收的内部数字信号可以被转换为交换机上的模拟输出信号。 然后可以根据串行数据协议将经转换的模拟输出信号发送到外部目的地。

公开(公告)号：US07955885B1

公开(公告)日：2011-06-07

申请号：US12351020

申请日：2009-01-09

申请人： Harmeet Bhugra ,  Kuolung Lei ,  Ye Wang

发明人： Harmeet Bhugra ,  Kuolung Lei ,  Ye Wang

IPC分类号： H01L21/00 ,  H01L21/30 ,  H01L21/46

CPC分类号： B81C1/00301 ,  B81B2207/095 ,  B81C2203/0118

摘要： Methods of forming packaged micro-electromechanical devices include forming a first substrate having a micro-electromechanical device therein, which extends adjacent a first surface of the first substrate. A first surface of a second substrate is then bonded to the first surface of the first substrate, to thereby encapsulate the micro-electromechanical device within a space provided between the first and second substrates. Subsequent to bonding, a second surface of the second substrate is selectively etched to define at least one through-substrate opening therein, which exposes an electrode of the micro-electromechanical device. Thereafter, the through-substrate opening is filled with an electrically conductive through-substrate via.

摘要翻译： 形成包装的微机电装置的方法包括在其中形成具有微机电装置的第一基板，其在第一基板的第一表面附近延伸。 然后将第二基板的第一表面接合到第一基板的第一表面，从而将微机电装置封装在设置在第一和第二基板之间的空间内。 在接合之后，选择性地蚀刻第二衬底的第二表面以在其中限定其中暴露微机电器件的电极的至少一个贯穿衬底开口。 此后，贯通基板开口填充有导电贯穿基板通孔。