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公开(公告)号：US08391302B1
公开(公告)日：2013-03-05
申请号：US12630811
申请日：2009-12-03
IPC分类号： G01R31/08 , G06F11/00 , G08C15/00 , H04J1/16 , H04J3/14 , H04L1/00 , H04L12/26 , H04L12/28 , H04L12/56
CPC分类号： H04L47/10 , H04L1/0026 , H04L1/0027 , H04L49/9015 , H04L49/9042 , H04L2001/0093
摘要： A packet switch includes ingress ports, each of which contains a random access memory having a storage capacity for storing data. An ingress controller of the packet switch allocates the storage capacity of each random access memory among transaction types of packets by allocating credits to each of the transactions types for the random access memory. Each ingress port accepts packets based on the transaction types of the packets and the credits of the random access memory in the ingress port. Moreover, the ingress port stores accepted packets in the random access memory of the ingress port. In further embodiments, the ingress controller dynamically reallocates the credits of the random access memory in the ingress port during operation of the packet switch.
摘要翻译： 分组交换机包括入口端口，每个端口包含具有用于存储数据的存储容量的随机存取存储器。 分组交换机的入口控制器通过向随机存取存储器的每个事务类型分配信用来分配每个随机存取存储器的数据包的事务类型的存储容量。 每个入口端口根据报文的事务类型和入口端口随机访问存储器的信用接受数据包。 此外，入口端口将接受的包存储在入口端口的随机存取存储器中。 在进一步的实施例中，入口控制器在分组交换机的操作期间动态地重新分配入口端口中的随机存取存储器的信用。
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公开(公告)号：US08400915B1
公开(公告)日：2013-03-19
申请号：US12710592
申请日：2010-02-23
CPC分类号： H04L47/39
摘要： A packet switch includes a pipeline scheduler for scheduling packets according to a credit-based flow control protocol. A credit update pipeline stage initializes available credits for egress ports of the packet switch. A request pipeline stage generates packet requests for packets based on the available credits. A grant pipeline stage selects packets based on the ports requests and the available credits, and generates port grants for the selected packets. Additionally, the credit update stage updates the available credits based on the port grants. The packet switch routes the selected packets from ingress ports of the packet switch to the egress ports based on the port grants. In some embodiments, ingress ports generate enqueue requests based on the packets, an enqueue pipeline stage generates enqueue states based on the enqueue requests, and the request pipeline stage selects packets for routing based on the enqueue states and the available credits.
摘要翻译： 分组交换机包括用于根据基于信用的流控制协议来调度分组的流水线调度器。 信用更新流水线阶段初始化分组交换机出口端口的可用信用。 请求流水线阶段基于可用的信用来生成分组的分组请求。 授权流水线阶段基于端口请求和可用信用来选择分组，并为所选择的分组生成端口许可。 此外，信用更新阶段根据端口许可更新可用信用。 分组交换机基于端口授权，将选择的分组从分组交换机的入口端口路由到出口端口。 在一些实施例中，入口端口基于分组生成入队请求，入队流水线阶段基于入队请求生成入队状态，并且请求流水线级基于入队状态和可用信用来选择用于路由的分组。
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公开(公告)号：US08284790B1
公开(公告)日：2012-10-09
申请号：US12701472
申请日：2010-02-05
IPC分类号： H04L12/56
CPC分类号： H04L49/506 , H04L47/33 , H04L47/566 , H04L47/6205 , H04L49/3018 , H04L49/508
摘要： A packet switch receives packets at an ingress port, generates enqueue records for the packets, and stores the enqueue records in an enqueue structure. The enqueue record of a packet includes a pass flag for indicating whether a permissive passing rule is applicable to the packet. The packet switch determines a routing order for the packets stored in the ingress port based on the enqueue records and a set of ordering rules including the permissive passing rule. If a packet is blocked in the packet switch, the packet switch identifies an oldest unblocked routable packet stored in the ingress port based on the enqueue records and the set of ordering rules. Further, the packet switch routes the oldest unblocked routable packet through the packet switch. In this way, the packet switch allows the oldest unblocked routable packet to pass the blocked packet in the packet switch.
摘要翻译： 分组交换机在入口端口接收分组，生成分组的入库记录，并将入库记录存储在入队结构中。 分组的入队记录包括用于指示允许通过规则是否适用于分组的通过标志。 分组交换机基于入队记录和包括允许通过规则的一组排序规则来确定存储在入口端口中的分组的路由顺序。 如果分组交换机中的分组被阻塞，则分组交换机基于入队记录和排序规则集来识别存储在入口端口中的最旧的未阻塞可路由分组。 此外，分组交换机通过分组交换机路由最旧的未阻塞可路由分组。 以这种方式，分组交换机允许最早的未阻塞可路由分组通过分组交换机中的阻塞分组。
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公开(公告)号：US08174969B1
公开(公告)日：2012-05-08
申请号：US12625491
申请日：2009-11-24
IPC分类号： H04L12/26
CPC分类号： H04L49/50
摘要： A packet switch includes a flow control circuit for preventing a downstream ingress port of the packet switch from providing a non-posted packet to an upstream egress port of the packet switch when a downstream egress port of the packet switch is congested. As a result, congestion is reduced in the downstream egress port. Additionally, congestion is reduced in an upstream ingress port of the packet switch that receives completion packets in response to non-posted packets output from the upstream egress port and provides the completion packets to the downstream egress port. Because congestion is reduced in the upstream ingress port, latency is reduced for a completion packet received at the upstream ingress port and provided to another downstream egress port of the packet switch in response to a non-posted packet provided from another downstream ingress port to the upstream egress port and output from the packet switch.
摘要翻译： 分组交换机包括流控制电路，用于当分组交换机的下游出口端口拥塞时，防止分组交换机的下游进入端口向分组交换机的上游出口端口提供非分支分组。 结果，下游出口端口拥塞减少。 此外，响应于从上游出口端口输出的非发布分组，接收完成分组的分组交换机的上游入口端口的拥塞减少，并向下游出口端口提供完成分组。 由于上游入口端口的拥塞减少，所以在上游入口端口接收到的完成分组的延迟会减少，并且响应于从另一个下游进入端口提供的非发布分组提供给分组交换机的另一个下游出口端口 上行出口端口和分组交换机的输出。
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公开(公告)号：US08599913B1
公开(公告)日：2013-12-03
申请号：US13195685
申请日：2011-08-01
申请人： David Alan Brown , Dzung Tran
发明人： David Alan Brown , Dzung Tran
CPC分类号： G06F13/4027 , Y02D10/14 , Y02D10/151
摘要： A data regeneration device regenerates a digital signal in a low-speed pass-through mode of operation, performs an upstream link equalization procedure on an upstream data link in an equalization mode of operation, performs a downstream link equalization procedure on a downstream data link in the equalization mode of operation, and regenerates the digital signal in a high-speed pass-through mode of operation. The data regeneration device transitions seamlessly from the low-speed pass-through mode of operation to the equalization mode of operation in compliance with a communication protocol. Moreover, the data regeneration device synchronizes completion of the upstream link equalization procedure with completion of the downstream link equalization procedure so that the data regeneration device transitions seamlessly from the equalization mode of operation to the high-speed pass-through mode of operation in compliance with the communication protocol.
摘要翻译： 数据再生装置以低速直通操作模式再生数字信号，在均衡操作模式下对上游数据链路执行上行链路均衡处理，对下游数据链路进行下行链路均衡处理 均衡操作模式，并以高速直通操作模式再生数字信号。 数据再生装置根据通信协议从低速直通操作模式无缝转换到均衡操作模式。 此外，数据再生装置使上行链路均衡处理的完成与下行链路均衡处理的完成同步，使得数据再生装置从均衡操作模式到高速直通操作模式无缝地转换，符合 通信协议。
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公开(公告)号：US08539275B2
公开(公告)日：2013-09-17
申请号：US13028139
申请日：2011-02-15
CPC分类号： G06F1/28 , G06F1/04 , G06F1/06 , G06F1/12 , G06F1/22 , G06F9/4403 , G06F13/4291 , G09G3/3406 , G09G5/10 , G09G2320/0233 , H05B33/0803 , H05B33/0815 , H05B33/0851
摘要： A single wire serial interface for power ICs and other devices is provided. To use the interface, a device is configured to include an EN/SET input pin. A counter within the device counts clock pulses sent to the EN/SET input pin. The output of the counter is passed to a ROM or other decoder circuit. The ROM selects an operational state for the device that corresponds to the value of the counter. In this way, control states may be selected for the device by sending corresponding clock pulses to the EN/SET pin. Holding the EN/SET pin high causes the device to maintain its operational state. Holding the EN/SET pin low for a predetermined timeout period resets the counter and causes the device to adopt a predetermined configuration (such as off) until new clock pulses are received at the EN/SET pin.
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公开(公告)号：US06850048B2
公开(公告)日：2005-02-01
申请号：US10428095
申请日：2003-05-02
申请人： Raymond Kenneth Orr , Yan-Fei Liu , Roger Peter Colbeck , David Alan Brown , Hartley Fred Horwitz
发明人： Raymond Kenneth Orr , Yan-Fei Liu , Roger Peter Colbeck , David Alan Brown , Hartley Fred Horwitz
CPC分类号： H02M3/33569 , H02M2001/0012 , H02M2001/008
摘要： A power supply controller controls power supplies for power-up and/or shut-down in a desired sequence. An input voltage for the power supplies powers, and is monitored by, a first control unit having outputs for enabling the power supplies. A second control unit monitors output voltages of the power supplies, and an isolating signal coupler couples signals in both directions between the first and second control units. The second control unit is powered in an isolated manner from the input voltage, conveniently via a transformer constituting the signal coupler. The control units together respond to the monitored voltages for enabling the power supplies in accordance with the desired sequence, information for which can be stored in a non-volatile store. The second control unit can also include enable outputs isolated from the input voltage, and trim outputs for adjusting the monitored voltages.
摘要翻译： 电源控制器以所需的顺序控制上电和/或关闭的电源。 用于电源的输入电压由具有用于启用电源的输出的第一控制单元供电并被监控。 第二控制单元监视电源的输出电压，并且隔离信号耦合器在第一和第二控制单元之间沿两个方向耦合信号。 第二控制单元通过构成信号耦合器的变压器，与输入电压隔离的方式供电。 控制单元一起响应所监视的电压，以根据期望的顺序启用电源，其信息可以存储在非易失性存储器中。 第二控制单元还可以包括与输入电压隔离的使能输出，以及调整输出以调整所监视的电压。
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公开(公告)号：US06415002B1
公开(公告)日：2002-07-02
申请号：US09056841
申请日：1998-04-07
IPC分类号： H04L2720
CPC分类号： H03C3/0975 , H03C3/40 , H03C5/00 , H04L27/2017
摘要： A baseband signal modulator provides a phase and amplitude modulated carrier signal. First and second phase modulators each receive a common reference signal and derive therefrom a carrier signal frequency. The phase modulators each receive a respective pair of phase-encoded data signals so as to provide respective first and second phase-encoded carrier. The modulator outputs are summed to provide the phase and amplitude modulated carrier signal. Each phase modulator includes a respective phase locked loop incorporating an oscillator locked via the common reference signal to the carrier signal frequency, and a phase adder having a first input for receiving the carrier frequency signal and having second and third inputs for receiving the respective pair of data encoded signals.
摘要翻译： 基带信号调制器提供相位和幅度调制载波信号。 第一和第二相位调制器各自接收公共参考信号并由此导出载波信号频率。 相位调制器各自接收相应的一对相位编码数据信号，以便提供相应的第一和第二相位编码载波。 将调制器输出相加以提供相位和幅度调制载波信号。 每个相位调制器包括相应的锁相环，该锁相环包括通过公共参考信号锁定到载波信号频率的振荡器，以及相位加法器，具有用于接收载波频率信号的第一输入端，并具有第二和第三输入端，用于接收相应的一对 数据编码信号。
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公开(公告)号：US08295293B1
公开(公告)日：2012-10-23
申请号：US12639938
申请日：2009-12-16
申请人： David Alan Brown
发明人： David Alan Brown
CPC分类号： H04L47/39 , H04L49/506
摘要： A packet switch issues credits to a link partner based on credit values and updates the credit values to indicate credits consumed by the link partner based on packets received from the link partner by the ingress port. Additionally, the packet switch selects credit threshold values corresponding to a transmission period of imminent credit starvation of the link partner and compares the updated credit values with the credit threshold values. The packet switch issues additional credits to the link partner when at least one of the updated credit values has reached a corresponding credit threshold value. In some embodiments, the packet switch also issues additional credits to the link partner during idle transmission periods.
摘要翻译： 分组交换机基于信用值向链路伙伴发出信用，并且更新信用值，以基于由入口端口从链路伙伴接收到的分组来指示链路伙伴消耗的信用。 此外，分组交换机选择对应于链路伙伴即将发生的信用不足的传输周期的信用阈值，并将更新的信用值与信用阈值进行比较。 当至少一个更新的信用值已经达到相应的信用阈值时，分组交换机向链路伙伴发出额外的信用。 在一些实施例中，分组交换机还在空闲传输周期期间向链路伙伴发出额外的信用。
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公开(公告)号：US20110202787A1
公开(公告)日：2011-08-18
申请号：US13028139
申请日：2011-02-15
IPC分类号： G06F1/04
CPC分类号： G06F1/28 , G06F1/04 , G06F1/06 , G06F1/12 , G06F1/22 , G06F9/4403 , G06F13/4291 , G09G3/3406 , G09G5/10 , G09G2320/0233 , H05B33/0803 , H05B33/0815 , H05B33/0851
摘要： A single wire serial interface for power ICs and other devices is provided. To use the interface, a device is configured to include an EN/SET input pin. A counter within the device counts clock pulses sent to the EN/SET input pin. The output of the counter is passed to a ROM or other decoder circuit. The ROM selects an operational state for the device that corresponds to the value of the counter. In this way, control states may be selected for the device by sending corresponding clock pulses to the EN/SET pin. Holding the EN/SET pin high causes the device to maintain its operational state. Holding the EN/SET pin low for a predetermined timeout period resets the counter and causes the device to adopt a predetermined configuration (such as off) until new clock pulses are received at the EN/SET pin.
摘要翻译： 提供了用于电源IC和其他设备的单线串行接口。 要使用该接口，设备配置为包含一个EN / SET输入引脚。 器件内的计数器计数发送到EN / SET输入引脚的时钟脉冲。 计数器的输出传递给ROM或其他解码器电路。 ROM选择与计数器的值相对应的设备的操作状态。 以这种方式，可以通过向EN / SET引脚发送相应的时钟脉冲来为器件选择控制状态。 将EN / SET引脚保持为高电平使器件保持其工作状态。 将EN / SET引脚保持低电平达预定的超时周期，复位计数器，并使器件采取预定的配置（如关闭），直到在EN / SET引脚接收到新的时钟脉冲。
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