公开(公告)号：US07425812B2

公开(公告)日：2008-09-16

申请号：US11343637

申请日：2006-01-30

Applicant: Randy B. Goldberg

Inventor： Randy B. Goldberg

IPC: G05B11/42

CPC classification number: G06F1/206

Abstract: A fan controller may be integrated in silicon and may use an embedded microcontroller to implement a digital fan control algorithm. The microcontroller may continually monitor temperature and sample the speed of the controlled fan. The speed of the fan may be compared to RPM values fitted on a desired curve that is representative of the Temperature-versus-RPM function for the controlled fan. The fan control algorithm may be based on a ramp-rate closed-loop controller (RRCC), which may be operated to drive the fan to the desired speed at different rates, depending on the difference between the desired RPM and the actual RPM of the fan. The fan may also provide a Fan ID feedback signal to the microcontroller, which may use the Fan ID feedback signal upon system start-up to initialize the RRCC range settings and select the appropriate Temperature-versus-RPM function curve based on pre-determined values for the given fan.

Abstract translation: 风扇控制器可以集成在硅中，并且可以使用嵌入式微控制器来实现数字风扇控制算法。 微控制器可以连续监测受控风扇的温度和速度。 风扇的速度可以与安装在所需曲线上的RPM值进行比较，该曲线代表受控风扇的温度对RPM功能。 风扇控制算法可以基于斜坡率闭环控制器（RRCC），其可以被操作以根据所需RPM与实际RPM之间的差异以不同的速率驱动风扇达到所需速度 风扇。 风扇还可以向微控制器提供风扇ID反馈信号，其可以在系统启动时使用风扇ID反馈信号来初始化RRCC范围设置，并且基于预定值选择适当的温度对RPM功能曲线 对于给定的风扇

公开(公告)号：US07415260B2

公开(公告)日：2008-08-19

申请号：US10795740

申请日：2004-03-08

Applicant: Troy L. Stockstad ,  Klaas Wortel ,  Luis J. Briones ,  David Lovelace

Inventor： Troy L. Stockstad ,  Klaas Wortel ,  Luis J. Briones ,  David Lovelace

IPC: H04B1/00

CPC classification number: H04B1/30

Abstract: A current-mode direct conversion RF receiver is presented. In one set of embodiments the RF receiver comprises a simple transconductor input stage to create a current-mode modulated signal from a voltage-mode modulated signal. A downconversion mixer may be coupled to the transconductor input stage via a low impedance current cascode stage, and may operate to create a set of current-mode quadrature baseband signals from the current-mode modulated signal. The downconversion mixer may be implemented with a transistor-switching network, which may be driven by a phase locked loop (PLL) with quadrature outputs. The set of current-mode quadrature baseband signals may be converted back to the voltage domain by a transimpedance filter, which may perform channel selection for the receiver. The transimpedance filter may additionally include a low frequency zero to remove DC offsets. The receiver may be implemented using CMOS design technologies and operated with minimal self-mixing effects, minimal DC offset in the baseband signal, and utilizing low voltages.

Abstract translation: 提出了一种电流模式直接转换RF接收机。 在一组实施例中，RF接收机包括简单的跨导体输入级，以从电压模式调制信号产生电流模式调制信号。 下变频混频器可以经由低阻抗电流共源共栅级耦合到跨导体输入级，并且可以操作以从当前模式调制信号创建一组电流模式正交基带信号。 下变频混频器可以用晶体管切换网络来实现，其可以由具有正交输出的锁相环（PLL）来驱动。 电流模式正交基带信号的集合可以通过跨阻滤波器转换回电压域，该跨阻滤波器可以对接收机执行信道选择。 跨阻滤波器可以另外包括用于去除DC偏移的低频零点。 接收机可以使用CMOS设计技术来实现，并且以最小的自混合效应，基带信号中的最小DC偏移和利用低电压进行操作。

公开(公告)号：US07295897B2

公开(公告)日：2007-11-13

申请号：US10784837

申请日：2004-02-23

Applicant: Eileen M. Marando ,  Robert W. Schoepflin

Inventor： Eileen M. Marando ,  Robert W. Schoepflin

IPC: G01M1/38 ,  G05B13/00 ,  H02H7/08 ,  F24D5/14

CPC classification number: F04D27/00

Abstract: A fan control system in which a sensor selection block having a number of sensor inputs may be combined with an autofan block having a number of zone inputs, where the number of sensor inputs is greater than the number of zone inputs. Each one of the sensor inputs of the sensor selection block may have a corresponding sensor parameter input. The sensor selection block may be configured to map a subset of the sensor inputs with corresponding sensor parameter inputs to the autofan block. Each zone input and corresponding zone parameter input of the autofan block may receive a corresponding one of the subset of the sensor inputs with corresponding sensor parameter inputs, respectively. The autofan block may have a number of pulse width modulated (PWM) outputs that may be calculated according to the autofan block zone inputs and zone parameter inputs.

Abstract translation: 一种风扇控制系统，其中具有多个传感器输入的传感器选择块可以与具有多个区域输入的自动扇区组合，其中传感器输入的数量大于区域输入的数量。 传感器选择块的传感器输入中的每一个可以具有相应的传感器参数输入。 传感器选择块可以被配置为将传感器输入的子集与相应的传感器参数输入映射到自动模块。 自动扇区块的每个区域输入和相应的区域参数输入可以分别接收相应的传感器输入的传感器输入的子集中的对应的一个。 自动模块可以具有多个脉冲宽度调制（PWM）输出，可根据自动模块区域输入和区域参数输入进行计算。

公开(公告)号：US20070260804A1

公开(公告)日：2007-11-08

申请号：US11417391

申请日：2006-05-03

Applicant: Drew Dutton ,  Alan Berenbaum ,  Raphael Weiss

Inventor： Drew Dutton ,  Alan Berenbaum ,  Raphael Weiss

IPC: G06F13/36

CPC classification number: G06F13/4027

Abstract: A system including a serialized secondary bus architecture. The system may include an LPC bus, an I/O controller, a serialized secondary bus, and at least one slave device. The LPC bus may be connected to the I/O controller, and the at least one slave device may be connected to the I/O controller via the serialized secondary bus. The serialized secondary bus has a reduced pin count relative to the LPC bus. The I/O controller may receive bus transactions from the LPC bus. The I/O controller may translate and forward LPC bus transactions to the at least one device over the secondary bus. The I/O controller may include a processing unit. The processing unit may initiate bus transactions intended for the at least one slave device. The I/O controller may also include a bus arbitration unit. The bus arbitration unit may arbitrate ownership of the secondary bus between the processing unit and the LPC bus.

Abstract translation: 一种包括序列化二次总线架构的系统。 该系统可以包括LPC总线，I / O控制器，串行化辅助总线和至少一个从设备。 LPC总线可以连接到I / O控制器，并且至少一个从设备可以经由串行辅助总线连接到I / O控制器。 串行次级总线相对于LPC总线的引脚数量减少。 I / O控制器可以从LPC总线接收总线事务。 I / O控制器可以通过辅助总线将LPC总线事务转换和转发到至少一个设备。 I / O控制器可以包括处理单元。 处理单元可以启动用于至少一个从设备的总线事务。 I / O控制器还可以包括总线仲裁单元。 总线仲裁单元可以仲裁处理单元和LPC总线之间的辅助总线的所有权。

公开(公告)号：US20070257644A1

公开(公告)日：2007-11-08

申请号：US11429098

申请日：2006-05-05

Applicant: Scott McLeod

Inventor： Scott McLeod

IPC: G05F1/00

CPC classification number: G05F1/565

Abstract: A voltage regulator may include a resistor-based voltage divider circuit generating a desired output voltage from a supply voltage, an output NMOS device whose source terminal may be configured as the output of the voltage regulator and whose drain terminal may be configured to receive the supply voltage, and a control circuit configured to control the output NMOS device to maintain the desired output voltage at the output of the voltage regulator. The control circuit may be configured to receive the desired output voltage from the voltage divider circuit as a first input, and to receive the output of the voltage regulator fed back as a second input to form a feedback loop. The control circuit may control the gate of the output NMOS device via the feedback loop to adjust the output of the voltage regulator by maintaining the desired output voltage at the source of the output NMOS device, and may also clamp the output of the voltage regulator to a specified voltage that is lower than the supply voltage, without requiring a second feedback loop.

Abstract translation: 电压调节器可以包括从电源电压产生期望的输出电压的电阻器分压器电路，输出NMOS器件，其源极端子可以被配置为电压调节器的输出，并且其漏极端子可以被配置为接收电源 电压以及被配置为控制输出NMOS器件以在电压调节器的输出端保持期望的输出电压的控制电路。 控制电路可以被配置为从分压器电路接收期望的输出电压作为第一输入，并且接收作为第二输入反馈的电压调节器的输出以形成反馈回路。 控制电路可以经由反馈回路来控制输出NMOS器件的栅极，以通过在输出NMOS器件的源极处保持期望的输出电压来调节电压调节器的输出，并且还可以将电压调节器的输出钳位到 低于电源电压的指定电压，而不需要第二个反馈回路。

公开(公告)号：US20070255885A1

公开(公告)日：2007-11-01

申请号：US11412431

申请日：2006-04-27

Applicant: Mark Bohm ,  Donald Perkins ,  Carl Crawford

Inventor： Mark Bohm ,  Donald Perkins ,  Carl Crawford

IPC: G06F13/00

CPC classification number: G06F13/4022 ,  G06F2213/0042

Abstract: System and method for switching logic in a Universal Serial Bus hub. The USB hub may include upstream logic and downstream logic for sending and receiving information from a host controller and a USB device respectively. The USB hub may include a plurality of ports operable to couple to a plurality of devices, including a first port coupled to the upstream logic and a second port coupled to the downstream logic. The USB hub may also include switching logic operable to switch the upstream and the downstream logic with respect to the first port and the second port respectively. The switching logic may switch the upstream and downstream logic by decoupling the first port from the upstream logic, decoupling the second port from the downstream logic, and coupling the second port to the upstream logic. Additionally, the first port may be coupled to the downstream logic.

Abstract translation: 用于在通用串行总线集线器中切换逻辑的系统和方法。 USB集线器可以包括用于分别从主机控制器和USB设备发送和接收信息的上游逻辑和下游逻辑。 USB集线器可以包括多个可操作以耦合到多个设备的端口，包括耦合到上游逻辑的第一端口和耦合到下游逻辑的第二端口。 USB集线器还可以包括可操作以分别相对于第一端口和第二端口切换上游和下游逻辑的交换逻辑。 切换逻辑可以通过将第一端口与上游逻辑解耦来解耦上游和下游逻辑，将第二端口与下游逻辑解耦，并将第二端口耦合到上游逻辑。 另外，第一端口可以耦合到下游逻辑。

公开(公告)号：US20070192516A1

公开(公告)日：2007-08-16

申请号：US11355677

申请日：2006-02-16

Applicant: Sharif Ibrahim ,  William Mahany ,  Larisa Troyegubova ,  Bishnu Karki ,  Kenneth Smalley

Inventor： Sharif Ibrahim ,  William Mahany ,  Larisa Troyegubova ,  Bishnu Karki ,  Kenneth Smalley

IPC: G06F13/28

CPC classification number: G06F13/4054

Abstract: A virtual FIFO automatic data transfer mechanism. A processor unit may allocate memory space within system memory for a data transfer operation. The processing unit may also program both a source device and a target device to perform the data transfer operation. After the programming, the source and target devices perform the data transfer operation without intervention by the processing unit until completion. The source device may store data into the allocated memory space, and indicate to the target device when it has stored a predetermined number of data bytes into the allocated memory space. In response to receiving the notification message, the target device may read the stored data from the allocated memory space, and indicate to the source device when the target device has read a predetermined number of data bytes from the allocated memory space.

Abstract translation: 虚拟FIFO自动数据传输机制。 处理器单元可以在系统存储器内分配用于数据传输操作的存储器空间。 处理单元还可以对源设备和目标设备进行编程，以执行数据传输操作。 编程完成后，源和目标设备执行数据传输操作，无需处理单元进行干预，直到完成。 源设备可以将数据存储到分配的存储器空间中，并且当其已经将预定数量的数据字节存储到分配的存储器空间中时，向目标设备指示。 响应于接收到通知消息，目标设备可以从分配的存储器空间读取所存储的数据，并且当目标设备从分配的存储器空间读取预定数量的数据字节时向源设备指示。

公开(公告)号：US20070052473A1

公开(公告)日：2007-03-08

申请号：US11219071

申请日：2005-09-02

Applicant: Scott McLeod

Inventor： Scott McLeod

IPC: G05F1/10

CPC classification number: G05F3/30

Abstract: In one embodiment, a bandgap voltage reference generating circuit is configured to generate a reference voltage, and may comprise a first PN-junction whose base-emitter voltage (VBE) exhibits a curvature with respect to temperature, where a current conducted by the first PN-junction is proportional to absolute temperature (PTAT). The voltage reference generating circuit may also include a second PN-junction coupled to the first PN-junction. A control circuit coupled to the second PN-junction may be configured to inject a control current into the second PN-junction, where the control current has a negative to absolute temperature (NTAT) characteristic, the control circuit thereby operating to effectively eliminate a curvature with respect to temperature exhibited by the bandgap voltage.

Abstract translation: 在一个实施例中，带隙电压参考产生电路被配置为产生参考电压，并且可以包括第一PN结，其基极 - 发射极电压（V BAT）表现出相对于温度的曲率， 其中由第一PN结传导的电流与绝对温度（PTAT）成比例。 电压参考产生电路还可以包括耦合到第一PN结的第二PN结。 耦合到第二PN结的控制电路可以被配置为将控制电流注入到第二PN结中，其中控制电流具有负绝对温度（NTAT）特性，因此控制电路操作以有效地消除曲率 相对于由带隙电压显示的温度。

公开(公告)号：US20060276986A1

公开(公告)日：2006-12-07

申请号：US11145906

申请日：2005-06-06

Applicant: Thomas Anderson ,  William Castellano ,  Scott McLeod

Inventor： Thomas Anderson ,  William Castellano ,  Scott McLeod

IPC: G06F19/00

CPC classification number: G01R31/31703 ,  G01R31/3167

Abstract: In one set of embodiments, trimming of a reference, which may be a bandgap reference and which is configured on an integrated circuit, may be controlled by an algorithm executed by logic circuitry also configured on the integrated circuit. The bandgap reference may be configured to generate a reference voltage provided to an analog to digital converter (ADC) comprised in a temperature sensor that may also be configured on the integrated circuit. The logic circuitry may be configured to execute one or more of a variety of test algorithms, for example a Successive Approximation Method or remainder processing, that are operable to adjust values of reference trim bits used in trimming the bandgap reference. A tester system configured to perform testing of the integrated circuit may initiate execution of the test algorithm, thereby initiating the trimming process, and may wait for the test algorithm to complete within a previously defined amount of time, or may poll the logic circuitry to determine when the trimming process is complete.

Abstract translation: 在一组实施例中，可以通过由集成电路上也配置的逻辑电路执行的算法来控制可以是带隙基准并且在集成电路上配置的参考的修整。 带隙基准可以被配置为产生提供给也可以在集成电路上配置的温度传感器中的模数转换器（ADC）的参考电压。 逻辑电路可以被配置为执行各种测试算法中的一个或多个，例如连续逼近方法或余数处理，其可操作以调整在修整带隙基准中使用的参考修整位的值。 配置为执行集成电路的测试的测试器系统可以启动测试算法的执行，从而启动修剪过程，并且可以等待测试算法在先前定义的时间量内完成，或者可以轮询逻辑电路以确定 修剪过程完成。

公开(公告)号：US07086583B2

公开(公告)日：2006-08-08

申请号：US10762684

申请日：2004-01-20

Applicant: Henry Wurzburg

Inventor： Henry Wurzburg

IPC: G06F17/00

CPC classification number: G06K19/07732 ,  G06K7/0013 ,  G06K7/0086 ,  G06K19/0701

Abstract: In some embodiments, if a card in a card reader has not been accessed in a first specified amount of time, the card may be powered down. The card may be powered back up if an attempt is made to access the card. In some embodiments, if a memory card is in the memory card slot of the card reader, but has not been accessed in a second specified amount of time, the card reader may be electrically disconnected from the host controller if a sideband signal is available to signal the card reader when to electrically reconnect.

Abstract translation: 在一些实施例中，如果读卡器中的卡在第一指定的时间量内未被访问，则该卡可以断电。 如果尝试访问该卡，该卡可能会重新启动。 在一些实施例中，如果存储卡位于读卡器的存储卡插槽中，但是在第二规定时间内未被访问，则如果边带信号可用于读卡器，则读卡器可能与主机控制器电断开 在读卡器电连接时发出信号。