公开(公告)号：US5748921A

公开(公告)日：1998-05-05

申请号：US570591

申请日：1995-12-11

Applicant: Andy Lambrecht ,  Steve L. Belt ,  Drew Dutton

Inventor： Andy Lambrecht ,  Steve L. Belt ,  Drew Dutton

IPC: G06F13/16 ,  G06F13/14

CPC classification number: G06F13/1684

Abstract: A computer system including a plurality of multimedia devices each having a high-speed memory data channel for accessing system memory. Each multimedia device has a high speed link directly to system memory, which is preferably single or multiple ported memory. These individual links are preferably high speed serial interconnects but, alternatively, may be 4-bit, 8-bit, 16-bit, 24-bit, 32-bit, 64-bit or any combination thereof. In this embodiment, intelligent buffering is preferably implemented within the core logic, and arbitration for access to main memory is preferably implemented within the core logic. Each of the multimedia devices uses its dedicated memory data channel to perform data accesses and transfers directly to the main memory, bypassing PCI bus arbitration and PCI bus cycles. Alternatively, each of the multimedia devices includes a high speed memory channel directly to the memory controller in the core logic for accessing system memory. The computer system is thus optimized for real-time applications and provides increased performance over current computer architectures.

Abstract translation: 一种包括多个多媒体设备的计算机系统，每个多媒体设备具有用于访问系统存储器的高速存储器数据通道。 每个多媒体设备具有直接到系统存储器的高速链路，其优选地是单个或多个端口存储器。 这些单独的链路优选地是高速串行互连，但是也可以是4位，8位，16位，24位，32位，64位或其任何组合。 在本实施例中，优选地在核心逻辑内部实现智能缓存，并且优选地在核心逻辑内实现用于访问主存储器的仲裁。 每个多媒体设备使用其专用存储器数据信道来执行数据访问并直接传送到主存储器，绕过PCI总线仲裁和PCI总线周期。 或者，每个多媒体设备包括用于访问系统存储器的用于核心逻辑中的存储器控​​制器的高速存储器通道。 因此，计算机系统针对实时应用进行了优化，并提供了超过当前计算机体系结构的性能。

公开(公告)号：US5740387A

公开(公告)日：1998-04-14

申请号：US649539

申请日：1996-05-17

Applicant: Andy Lambrecht ,  Drew Dutton

Inventor： Andy Lambrecht ,  Drew Dutton

IPC: G06F13/12 ,  G06F13/36 ,  G06F13/368 ,  G06F13/372 ,  G06F13/40 ,  H04N21/238 ,  G06F13/00

CPC classification number: H04N21/238 ,  G06F13/124 ,  G06F13/36 ,  G06F13/368 ,  G06F13/372 ,  G06F13/4013 ,  G06F13/4022 ,  G06F13/4027

Abstract: A computer system optimized for real-time applications which provides increased performance over current computer architectures. The system includes a standard local system bus or expansion bus, such as the PCI bus, and also includes a dedicated real-time bus or multimedia bus. Various multimedia devices are coupled to one or more of the expansion bus and/or the multimedia bus. The computer system expansion bus implements a new mode of operation specifically for real-time transfers. A real time signal is used to indicate that the expansion bus should be placed in a special real time mode. When not in special real time mode, the expansion bus operates as usual. The real time mode is optimized for the transfer of high bandwidth real-time information. The computer system of the present invention thus provides much greater performance for real-time applications than prior systems.

Abstract translation: 针对实时应用程序进行了优化的计算机系统，提高了当前计算机体系结构的性能。 该系统包括标准本地系统总线或扩展总线，如PCI总线，还包括一个专用的实时总线或多媒体总线。 各种多媒体设备耦合到一个或多个扩展总线和/或多媒体总线。 计算机系统扩展总线实现专门用于实时传输的新的操作模式。 使用实时信号来指示扩展总线应该处于特殊的实时模式。 当不是在特殊的实时模式下，扩展总线按照常规运行。 实时模式针对传输高带宽实时信息进行了优化。 因此，本发明的计算机系统为实时应用提供比现有系统更大的性能。

公开(公告)号：US20070260804A1

公开(公告)日：2007-11-08

申请号：US11417391

申请日：2006-05-03

Applicant: Drew Dutton ,  Alan Berenbaum ,  Raphael Weiss

Inventor： Drew Dutton ,  Alan Berenbaum ,  Raphael Weiss

IPC: G06F13/36

CPC classification number: G06F13/4027

Abstract: A system including a serialized secondary bus architecture. The system may include an LPC bus, an I/O controller, a serialized secondary bus, and at least one slave device. The LPC bus may be connected to the I/O controller, and the at least one slave device may be connected to the I/O controller via the serialized secondary bus. The serialized secondary bus has a reduced pin count relative to the LPC bus. The I/O controller may receive bus transactions from the LPC bus. The I/O controller may translate and forward LPC bus transactions to the at least one device over the secondary bus. The I/O controller may include a processing unit. The processing unit may initiate bus transactions intended for the at least one slave device. The I/O controller may also include a bus arbitration unit. The bus arbitration unit may arbitrate ownership of the secondary bus between the processing unit and the LPC bus.

Abstract translation: 一种包括序列化二次总线架构的系统。 该系统可以包括LPC总线，I / O控制器，串行化辅助总线和至少一个从设备。 LPC总线可以连接到I / O控制器，并且至少一个从设备可以经由串行辅助总线连接到I / O控制器。 串行次级总线相对于LPC总线的引脚数量减少。 I / O控制器可以从LPC总线接收总线事务。 I / O控制器可以通过辅助总线将LPC总线事务转换和转发到至少一个设备。 I / O控制器可以包括处理单元。 处理单元可以启动用于至少一个从设备的总线事务。 I / O控制器还可以包括总线仲裁单元。 总线仲裁单元可以仲裁处理单元和LPC总线之间的辅助总线的所有权。

公开(公告)号：US20070162778A1

公开(公告)日：2007-07-12

申请号：US11674450

申请日：2007-02-13

Applicant: Drew Dutton ,  James MacDonald ,  Stephen Cox

Inventor： Drew Dutton ,  James MacDonald ,  Stephen Cox

IPC: G06F1/00

CPC classification number: G06F1/3215

Abstract: A system and method for monitoring usage of peripheral devices and placing a second peripheral device in a low power state when the usage indicates that a second peripheral device is not being used. For example, if a computer system detects that a user's current typing rate indicates the user probably has both hands on a keyboard, the computer system may generate a signal to the computer mouse to enter a low power state. The computer system may use prior usage for a user to determine when current usage indicates that the second peripheral device is not being used. After the second peripheral device is placed in a low power state, the computer system may generate a signal to the second peripheral device to return to a normal power state when the computer system determines that the user no longer has both hands occupied.

Abstract translation: 一种用于监视外围设备的使用并且当使用指示没有使用第二外围设备时将第二外围设备置于低功率状态的系统和方法。 例如，如果计算机系统检测到用户的当前打字率指示用户可能在键盘上具有双手，则计算机系统可以向计算机鼠标生成信号以进入低功率状态。 计算机系统可以使用用户的先前使用来确定当前使用情况何时指示第二外围设备未被使用。 在第二外围设备处于低功率状态之后，当计算机系统确定用户不再具有双手时，计算机系统可以向第二外围设备产生信号以返回到正常的功率状态。

公开(公告)号：US20060227759A1

公开(公告)日：2006-10-12

申请号：US11424179

申请日：2006-06-14

Applicant: Mark Bohm ,  Mark Fu ,  Henry Wurzburg ,  James Bowles ,  Robert Hollingsworth ,  Drew Dutton ,  Akhlesh Nigam

Inventor： Mark Bohm ,  Mark Fu ,  Henry Wurzburg ,  James Bowles ,  Robert Hollingsworth ,  Drew Dutton ,  Akhlesh Nigam

IPC: H04L12/28 ,  H04L12/56

CPC classification number: G06F13/4022 ,  G06F2213/4004

Abstract: In various embodiments, devices coupled to upstream ports may enumerate the USB switching hub according to the total number of downstream ports on the USB switching hub. In some embodiments, when a first upstream port is communicating with a first downstream port, status registers coupled to the second upstream port may indicate to the second upstream device that the first downstream port is disconnected. By enumerating the USB switching hub according to the total number of downstream ports, the upstream devices may not have to re-enumerate the hub (and correspondingly each device coupled to the hub) each time a downstream device is switched. In some embodiments, an intelligent port routing switch may delay switching communications for the downstream port if there is an active transfer in progress between a related downstream port and an upstream port.

Abstract translation: 在各种实施例中，耦合到上游端口的设备可以根据USB交换集线器上的下游端口的总数来枚举USB交换集线器。 在一些实施例中，当第一上游端口与第一下游端口通信时，耦合到第二上行端口的状态寄存器可以向第二上游设备指示第一下游端口被断开。 通过根据下游端口的总数枚举USB交换集线器，每次下游设备切换时，上游设备可能不必重新枚举集线器（以及相应的每个设备耦合到集线器）。 在一些实施例中，如果相关下游端口和上游端口之间存在正在进行的主动传输，则智能端口路由交换机可以延迟下游端口的交换通信。

公开(公告)号：US20060059293A1

公开(公告)日：2006-03-16

申请号：US10940406

申请日：2004-09-14

Applicant: Henry Wurzburg ,  James Bowles ,  Robert Hollingsworth ,  Mark Bohm ,  Drew Dutton

Inventor： Henry Wurzburg ,  James Bowles ,  Robert Hollingsworth ,  Mark Bohm ,  Drew Dutton

IPC: G06F13/20

CPC classification number: G06F13/4022 ,  G06F2213/4004

Abstract: In various embodiments, a USB switching hub may switch between a first configuration and a second configuration to switch access between two or more upstream ports on the hub to at least a subset of downstream ports on the hub. In some embodiments, the hub may include a downstream routing controller to switch between the first configuration and the second configuration. In some embodiments, configurations (e.g., hardwired in the USB switching hub) may be switched as determined by logic on the USB switching hub.

Abstract translation: 在各种实施例中，USB交换集线器可以在第一配置和第二配置之间切换，以将集线器上的两个或更多上游端口之间的接入切换到集线器上的下游端口的至少一个子集。 在一些实施例中，集线器可以包括下游路由控制器，以在第一配置和第二配置之间切换。 在一些实施例中，可以根据USB交换集线器上的逻辑来切换配置（例如，USB交换集线器中的硬连线）。

公开(公告)号：US20060056401A1

公开(公告)日：2006-03-16

申请号：US11100299

申请日：2005-04-06

Applicant: Mark Bohm ,  Mark Fu ,  Henry Wurzburg ,  James Bowles ,  Robert Hollingsworth ,  Drew Dutton

Inventor： Mark Bohm ,  Mark Fu ,  Henry Wurzburg ,  James Bowles ,  Robert Hollingsworth ,  Drew Dutton

IPC: H04L12/50

CPC classification number: G06F13/4022 ,  G06F2213/4004

Abstract: In various embodiments, devices coupled to upstream ports may enumerate the USB switching hub according to the total number of downstream ports on the USB switching hub. In some embodiments, when a first upstream port is communicating with a first downstream port, status registers coupled to the second upstream port may indicate to the second upstream device that the first downstream port is disconnected. By enumerating the USB switching hub according to the total number of downstream ports, the upstream devices may not have to reenumerate the hub (and correspondingly each device coupled to the hub) each time a downstream device is switched. In some embodiments, an intelligent port routing switch may delay switching communications for the downstream port if there is an active transfer in progress between a related downstream port and an upstream port.

Abstract translation: 在各种实施例中，耦合到上游端口的设备可以根据USB交换集线器上的下游端口的总数来枚举USB交换集线器。 在一些实施例中，当第一上游端口与第一下游端口通信时，耦合到第二上行端口的状态寄存器可以向第二上游设备指示第一下游端口被断开。 通过根据下游端口的总数枚举USB交换集线器，每次下游设备切换时，上游设备可能不必重新计算集线器（以及相应的每个设备耦合到集线器）。 在一些实施例中，如果相关下游端口和上游端口之间存在正在进行的主动传输，则智能端口路由交换机可以延迟下游端口的交换通信。

公开(公告)号：US20050160196A1

公开(公告)日：2005-07-21

申请号：US11071961

申请日：2005-03-04

Applicant: Drew Dutton ,  James MacDonald ,  Henry Wurzburg

Inventor： Drew Dutton ,  James MacDonald ,  Henry Wurzburg

IPC: G06F1/32 ,  G06K7/00 ,  G06K17/00 ,  G06F3/00

CPC classification number: G06K19/07732 ,  G06K7/0013 ,  G06K7/0086 ,  G06K19/0701

Abstract: In various embodiments, a computer system may include a computer controller to send and/or receive sideband signals to/from a USB device. In some embodiments, the USB device may include a USB controller to send/receive sideband signals to/from the computer controller. The computer controller and USB controller may allow communications between the computer system and the USB device when either of the computer system or USB device is in a low power state. The sideband signal sent between the computer system and the USB device may trigger the other of the computer system or USB device to enter a normal power state. In some embodiments, the computer controller and/or USB controller may be further coupled to a memory to buffer data to be sent to the computer system or USB device after the computer system or USB device returns to a normal power state.

Abstract translation: 在各种实施例中，计算机系统可以包括计算机控制器来向/从USB设备发送和/或接收边带信号。 在一些实施例中，USB设备可以包括用于向计算机控制器发送/接收边带信号的USB控制器。 当计算机系统或USB设备中的任一个处于低功率状态时，计算机控制器和USB控制器可以允许计算机系统和USB设备之间的通信。 在计算机系统和USB设备之间发送的边带信号可能触发计算机系统或USB设备中的另一个进入正常的电源状态。 在一些实施例中，计算机控制器和/或USB控制器可以进一步耦合到存储器，以在计算机系统或USB设备恢复到正常功率状态之后缓冲要发送到计算机系统或USB设备的数据。

公开(公告)号：US5754801A

公开(公告)日：1998-05-19

申请号：US650938

申请日：1996-05-17

Applicant: Andy Lambrecht ,  Scott Swanstrom ,  Drew Dutton

Inventor： Andy Lambrecht ,  Scott Swanstrom ,  Drew Dutton

IPC: G06F13/12 ,  G06F13/36 ,  G06F13/368 ,  G06F13/372 ,  G06F13/40 ,  H04N21/238 ,  H04N7/173 ,  G06F3/14 ,  G06F17/00

CPC classification number: G06F13/36 ,  G06F13/124 ,  G06F13/368 ,  G06F13/372 ,  G06F13/4022 ,  G06F13/4027 ,  H04N21/238

Abstract: A computer system optimized for real-time applications which provides increased performance over current computer architectures. The system includes a standard local system bus or expansion bus, such as the PCI bus, and also includes a dedicated real-time bus or multimedia bus. Various multimedia devices are coupled to one or more of the expansion bus and/or the multimedia bus. The computer system includes a dedicated or centralized I/O processor coupled to one or more of the expansion bus and/or the multimedia bus which operates to direct or pull stream information through the system. The centralized I/O processor comprises a memory for storing data rate, data periodicity, data source, and data destination information for the multimedia devices. The computer system of the present invention thus provides much greater performance for real-time applications than prior systems.

Abstract translation: 针对实时应用程序进行了优化的计算机系统，提高了当前计算机体系结构的性能。 该系统包括标准本地系统总线或扩展总线，如PCI总线，还包括一个专用的实时总线或多媒体总线。 各种多媒体设备耦合到一个或多个扩展总线和/或多媒体总线。 计算机系统包括耦合到一个或多个扩展总线和/或多媒体总线的专用或集中式I / O处理器，其操作以通过系统引导或引导流信息。 集中式I / O处理器包括用于存储用于多媒体设备的数据速率，数据周期，数据源和数据目的地信息的存储器。 因此，本发明的计算机系统为实时应用提供比现有系统更大的性能。

公开(公告)号：US5696927A

公开(公告)日：1997-12-09

申请号：US576100

申请日：1995-12-21

Applicant: James R. MacDonald ,  Drew Dutton ,  Steve Cox

Inventor： James R. MacDonald ,  Drew Dutton ,  Steve Cox

IPC: G06F12/02 ,  G06F12/08 ,  G06F12/10

CPC classification number: G06F12/023 ,  G06F12/08 ,  G06F12/1009 ,  G06F12/1027 ,  G06F2212/401

Abstract: A memory paging and compression system for a computer having a memory and an execution unit includes an address mapping hierarchy, a compressed page mapping hierarchy, a translation lookaside buffer, and a compression/decompression component. The address mapping hierarchy includes page tables having page table entries which map from a first portion of virtual addresses to respective pages in physical memory. The compressed page mapping hierarchy includes compressed page tables having compressed page table entries mapping from the first portion of virtual addresses to respective compressed pages in physical memory. The translation lookaside buffer caches recently used ones of the mappings from the first portion of virtual addresses to respective pages in physical memory. The compression/decompression component includes a compression/decompression engine coupled between a memory and an execution unit for alternately compressing and decompression pages in memory in respective correspondence with spills from and loads to the translation lookaside buffer. The address mapping hierarchy and compressed page mapping hierarchy may be represented in memory and the compression/decompression component may further include a decompression fault handler and a compression fault handler, each executable on the execution unit.

Abstract translation: 用于具有存储器和执行单元的计算机的存储器寻呼和压缩系统包括地址映射层级，压缩页面映射层级，翻译后端缓冲器和压缩/解压缩组件。 地址映射层次结构包括具有从虚拟地址的第一部分映射到物理存储器中的相应页面的页表条目的页表。 压缩页面映射层级包括具有从虚拟地址的第一部分映射到物理存储器中的相应压缩页面的压缩页表项的压缩页表。 翻译后备缓冲区最近缓存了从虚拟地址的第一部分到物理存储器中各页的映射关系。 压缩/解压缩部件包括耦合在存储器和执行单元之间的压缩/解压缩引擎，用于与存储器中的交替压缩和解压缩页面分别对应于来自翻译后备缓冲器的溢出和负载。 地址映射层级和压缩页映射层次可以在存储器中表示，并且压缩/解压缩组件还可以包括解压缩故障处理程序和压缩故障处理程序，每个执行单元都可执行。