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    First-in, first-out buffer
    92.
    发明授权
    First-in, first-out buffer 有权

    公开(公告)号：US12019569B1

    公开(公告)日：2024-06-25

    申请号：US18077286

    申请日：2022-12-08

    Applicant: Arm Limited

    Inventor： Julian Katenbrink

    IPC: G06F13/16

    CPC classification number: G06F13/1673 ,  G06F13/1689

    Abstract: An apparatus has first-in, first-out (FIFO) buffer circuitry to transfer data from a source domain to a sink domain across a clock domain boundary. The FIFO buffer circuitry has data transfer circuitry to store the data to be transferred across the clock domain boundary; and source and sink domain data transfer control circuitry to maintain respective state vectors indicative of a state of the FIFO buffer circuitry in the respective domain. At least one of the source domain transfer control circuitry and the sink domain transfer control circuitry is operable to perform a multi-item transfer to transfer two or more data items in a single clock cycle of a respective domain by placing the data items into, or reading the data items from, respective data storage elements; and advancing a state vector of the respective domain by two or more state vector encodings in the single clock cycle.

    Ray tracing graphics processing systems
    93.
    发明授权
    Ray tracing graphics processing systems 有权

    公开(公告)号：US12014456B2

    公开(公告)日：2024-06-18

    申请号：US17814387

    申请日：2022-07-22

    Applicant: Arm Limited

    Inventor： Edvard Fielding ,  Carmelo Giliberto

    IPC: G06T15/06 ,  G06T1/20 ,  G06T15/00 ,  G06T15/04 ,  G06T17/10

    CPC classification number: G06T15/06 ,  G06T1/20 ,  G06T15/005 ,  G06T15/04 ,  G06T17/10 ,  G06T2210/21

    Abstract: A method of operating a graphics processor when rendering a frame representing a view of a scene using a ray tracing process in which part of the processing for a ray tracing operation is offloaded to a texture mapper unit of the graphics processor. Thus, when the graphics processor's execution unit is executing a program to perform a ray tracing operation the execution unit is able to message the texture mapper unit to perform one or more processing operations for the ray tracing operation. This operation can be triggered by including an appropriate instruction to message the texture mapper unit within the ray tracing program.

    Apparatus and method of authorisation
    95.
    发明授权
    Apparatus and method of authorisation 有权

    公开(公告)号：US12002050B2

    公开(公告)日：2024-06-04

    申请号：US17251422

    申请日：2019-07-05

    Applicant: Arm Limited

    Inventor： Yongkang Liu

    IPC: G06Q20/40

    CPC classification number: G06Q20/40145

    Abstract: An apparatus adapted to authorise a transaction having a requested payment amount comprises receiving circuitry to receive a request to authorise the transaction, the request indicating the requested payment amount of the transaction, input circuitry to receive one or more user inputs required from the user to authorise the transaction and authorising circuitry to authorise the transaction when the one or more user inputs correspond to a user input payment amount that is the same as the requested payment amount of the transaction.

    Technique for controlling stashing of data
    96.
    发明授权
    Technique for controlling stashing of data 有权

    公开(公告)号：US12001722B2

    公开(公告)日：2024-06-04

    申请号：US17890456

    申请日：2022-08-18

    Applicant: Arm Limited

    Inventor： Pavel Shamis ,  Honnappa Nagarahalli ,  Jamshed Jalal

    IPC: G06F3/06

    CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0635 ,  G06F3/0673

    Abstract: There is provided an apparatus, method, and computer-readable medium. The apparatus comprises interconnect circuitry to couple a device to one or more processing elements and to one or more storage structures. The apparatus also comprises stashing circuitry configured to receive stashing transactions from the device, each stashing transaction comprising payload data and control data. The stashing circuitry is responsive to a given stashing transaction whose control data identifies a plurality of portions of the payload data, to perform a plurality of independent stashing decision operations, each of the plurality of independent stashing decision operations corresponding to a respective portion of the plurality of portions of payload data and comprising determining, with reference to the control data, whether to direct the respective portion to one of the one or more storage structures or whether to forward the respective portion to memory.

    Parameter signature for realm security configuration parameters
    97.
    发明授权
    Parameter signature for realm security configuration parameters 有权

    公开(公告)号：US12001541B2

    公开(公告)日：2024-06-04

    申请号：US17267193

    申请日：2019-09-05

    Applicant: Arm Limited

    Inventor： Nicholas Wood

    IPC: G06F21/62 ,  G06F12/14 ,  G06F21/51 ,  H04L9/32

    CPC classification number: G06F21/51 ,  G06F12/1458 ,  G06F21/62 ,  H04L9/3247 ,  G06F2212/1052 ,  G06F2221/033 ,  G06F2221/2145

    Abstract: Memory access circuitry 26 controls access to memory based on ownership information defining, for a given memory region, an owner realm specified from among two or more realms, each realm corresponding to at least a portion of a software processes miming on processing circuitry 8. The owner realm has a right to exclude other realms from accessing data stored within the given memory region. On activation of a target realm, it is detected whether a parameter signature derived from security configuration parameters established for the target realm matches an expected signature; and in response to detecting a mismatch between the parameter signature and the expected signature, an activation restriction is applied to the target realm to prevent the activation of target realm or prevent correct functioning of the target realm following activation.

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