公开(公告)号：US20060261398A1

公开(公告)日：2006-11-23

申请号：US11434175

申请日：2006-05-16

申请人： Chang-Hyun Lee

发明人： Chang-Hyun Lee

IPC分类号： H01L29/76

CPC分类号： H01L29/792 ,  H01L21/28282 ,  H01L21/823462 ,  H01L27/0629 ,  H01L27/105 ,  H01L27/11568 ,  H01L27/11573 ,  H01L28/20 ,  H01L29/4232

摘要： Disclosed is a nonvolatile memory device with cell and peripheral circuit regions confined on a substrate. Cell gate electrodes are arranged in the cell region while peripheral gate electrodes are arranged in the peripheral-circuit region. Each cell gate electrode includes stacked conductive and semiconductor layers, but the peripheral gate electrode includes stacked semiconductor layers. The conductive layer of the cell gate electrode is different from the lowest semiconductor layer of the peripheral gate electrode in material, which can improve characteristics of memory cells and peripheral transistors without causing mutual interference with each other.

摘要翻译： 公开了一种具有限制在基板上的单元和外围电路区域的非易失性存储器件。 电池栅电极配置在电池区域，而周边电极配置在外围电路区域。 每个单元栅极电极包括堆叠的导电和半导体层，但是外围栅电极包括堆叠的半导体层。 单元栅电极的导电层与材料中外围栅电极的最低半导体层不同，这可以改善存储单元和外围晶体管的特性，而不会相互干扰。

公开(公告)号：US07132331B2

公开(公告)日：2006-11-07

申请号：US10990903

申请日：2004-11-17

申请人： Young-Goan Jang ,  Chang-Hyun Lee ,  Jae-Hoon Kim

发明人： Young-Goan Jang ,  Chang-Hyun Lee ,  Jae-Hoon Kim

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  H01L21/76229 ,  H01L21/823481 ,  H01L27/115

摘要： A semiconductor device having a self-aligned gate conductive layer and a method of fabricating the same are disclosed. In embodiments of the present invention, a plurality of field isolation patterns are formed on a semiconductor substrate to define a plurality of active regions in the semiconductor substrate. The density of the field isolation patterns is then increased by, for example, a thermal annealing process. A plurality of gate insulation patterns are then formed on respective of the active regions. A plurality of first conductive patterns are then formed on respective of the gate insulation patterns.

摘要翻译： 公开了具有自对准栅极导电层的半导体器件及其制造方法。 在本发明的实施例中，在半导体衬底上形成多个场隔离图案以在半导体衬底中限定多个有源区。 然后通过例如热退火工艺增加场隔离图案的密度。 然后在相应的有源区上形成多个栅极绝缘图案。 然后在相应的栅极绝缘图案上形成多个第一导电图案。

公开(公告)号：US20060240612A1

公开(公告)日：2006-10-26

申请号：US11428884

申请日：2006-07-06

申请人： Chang-Hyun Lee

发明人： Chang-Hyun Lee

IPC分类号： H01L21/8238

CPC分类号： H01L27/105 ,  H01L27/11568 ,  H01L27/11573

摘要： A non-volatile memory device comprises a cell region defined at a substrate and a plurality of device isolation layers formed in the cell region to define a plurality of active regions. A charge storage insulator covers substantially the entire top surface of the cell region. A plurality of gate lines are formed on the charge storage insulator that cross over the device isolation layers. Conductive patterns are disposed between predetermined gate lines that penetrate the charge storage insulator to electrically connect with the active regions. According to the method of fabricating the device, a plurality of device isolation layers are formed in the substrate and then a charge storage insulator is formed on an entire surface of the substrate and the device isolation layers. A plurality of parallel gate lines that cross over the device isolation layers are formed on the charge storage insulator and then conductive patterns are formed between predetermined gate lines. The conductive patterns penetrate the charge storage insulator and electrically connect with the active regions.

摘要翻译： 非易失性存储器件包括限定在衬底处的单元区域和形成在单元区域中以限定多个有源区域的多个器件隔离层。 电荷存储绝缘体基本上覆盖电池区域的整个顶表面。 在电荷存储绝缘体上形成有跨越器件隔离层的多条栅极线。 导电图案设置在穿过电荷存储绝缘体的预定栅极线之间以与有源区电连接。 根据该器件的制造方法，在衬底中形成多个器件隔离层，然后在衬底和器件隔离层的整个表面上形成电荷存储绝缘体。 在电荷存储绝缘体上形成跨越器件隔离层的多条平行栅极线，然后在预定栅极线之间形成导电图案。 导电图案穿透电荷存储绝缘体并与有源区电连接。

公开(公告)号：US20060239083A1

公开(公告)日：2006-10-26

申请号：US11379752

申请日：2006-04-21

申请人： Chang-Hyun LEE

发明人： Chang-Hyun LEE

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A NAND flash memory device, and methods of forming and operating the same are provided. The NAND flash memory device includes first and second selection gate lines sequentially disposed at one side of a plurality of cell gate lines. A first selection transistor including the first selection gate line serves as a buffer for decreasing a highly boosted channel voltage of a non-selected cell to minimize the leakage current of the NAND flash memory device.

摘要翻译： 提供了一种NAND闪速存储器件及其形成和操作方法。 NAND闪存器件包括顺序地设置在多个单元栅极线的一侧的第一和第二选择栅极线。 包括第一选择栅极线的第一选择晶体管用作用于降低非选择单元的高度提升的沟道电压的缓冲器，以使NAND闪速存储器件的漏电流最小化。

公开(公告)号：US20060216891A1

公开(公告)日：2006-09-28

申请号：US11422592

申请日：2006-06-06

申请人： Jung-Dal CHOI ,  Jong-Woo PARK ,  Seong-Soon CHO ,  Chang-Hyun LEE

发明人： Jung-Dal CHOI ,  Jong-Woo PARK ,  Seong-Soon CHO ,  Chang-Hyun LEE

IPC分类号： H01L21/336

CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/11573

摘要： A non-volatile memory device includes a tunnel oxide layer, a charge storage layer, a blocking insulating layer, and a gate electrode that are sequentially stacked, as well as an impurity diffusion layer in an active region at both sides of the gate electrode. The gate electrode crosses active regions between device isolation layers formed in a predetermined area of a semiconductor substrate, and an edge of the charge storage layer is extended to have a protruding part that protrudes from the gate electrode. In order to form a charge storage layer having a protruding part, a stack insulating layer including first to third insulating layers is formed in an active region between the device isolation layers formed in the substrate. A plurality of gate electrodes crossing the active region are formed on the stack insulating layer, and a sidewall spacer is formed on both sidewalls of the gate electrode. Using the sidewall spacer and the gate electrode, the stack insulating layer is etched to form a charge storage layer that protrudes from the sidewall of the gate electrode.

摘要翻译： 非易失性存储器件包括依次层叠的隧道氧化物层，电荷存储层，阻挡绝缘层和栅电极，以及栅电极两侧的有源区中的杂质扩散层。 栅电极跨越形成在半导体衬底的预定区域中的器件隔离层之间的有源区，并且电荷存储层的边缘延伸成具有从栅电极突出的突出部分。 为了形成具有突出部分的电荷存储层，在形成在衬底中的器件隔离层之间的有源区域中形成包括第一至第三绝缘层的叠层绝缘层。 在堆叠绝缘层上形成与激活区交叉的多个栅电极，并且在栅电极的两个侧壁上形成侧墙。 使用侧壁间隔物和栅电极，对叠层绝缘层进行蚀刻以形成从栅电极的侧壁突出的电荷存储层。

公开(公告)号：US20060208338A1

公开(公告)日：2006-09-21

申请号：US11375983

申请日：2006-03-15

申请人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Chang-Seok Kang ,  Yoo-Cheol Shin ,  Jong-Sun Sel

发明人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Chang-Seok Kang ,  Yoo-Cheol Shin ,  Jong-Sun Sel

IPC分类号： H01L29/00

CPC分类号： H01L27/105 ,  B82Y10/00 ,  H01L21/823462 ,  H01L27/0629 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11568

摘要： Methods of forming a memory device include forming a device isolation layer in a semiconductor substrate including a cell array region and a resistor region, the device isolation layer extending into the resistor region and defining an active region in the semiconductor substrate. A first conductive layer is formed on the device isolation layer in the resistor region. The semiconductor substrate is exposed in the cell array region. A cell insulation layer is formed on a portion of the semiconductor substrate including the exposed cell array region, the active region and the device isolation layer in the resistor region. A second conductive layer is formed on the cell insulation layer in the portion of the semiconductor substrate including the exposed cell array region, the active region and the device isolation layer in the resistor region. The second conductive layer is etched to form a cell gate electrode in the cell array region and to concurrently remove the second conductive layer from the resistor region and the first conductive layer is etched in the resistor region to form a resistor.

摘要翻译： 形成存储器件的方法包括在包括单元阵列区域和电阻器区域的半导体衬底中形成器件隔离层，器件隔离层延伸到电阻器区域中并在半导体衬底中限定有源区域。 在电阻器区域中的器件隔离层上形成第一导电层。 半导体衬底暴露在电池阵列区域中。 在半导体衬底的包括电阻器区域中的暴露的电池阵列区域，有源区域和器件隔离层的部分上形成电池绝缘层。 在半导体衬底的包括电阻器区域中的暴露的电池阵列区域，有源区域和器件隔离层的部分中的单元绝缘层上形成第二导电层。 蚀刻第二导电层以在电池阵列区域中形成电池栅电极，并且同时从电阻器区域去除第二导电层，并且在电阻器区域中蚀刻第一导电层以形成电阻器。

公开(公告)号：US20060202263A1

公开(公告)日：2006-09-14

申请号：US11296479

申请日：2005-12-08

申请人： Chang-Hyun Lee

发明人： Chang-Hyun Lee

IPC分类号： H01L29/94

CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L29/42332 ,  H01L29/7881 ,  H01L29/792

摘要： In an example embodiment, a semiconductor substrate has a plurality of active regions separated by a plurality of trenches. A gate insulation film fills at least a portion of the trenches, and a conductive gate film is formed over the gate insulation film. In an example embodiment, the gate insulation film, may include a tunneling insulation film, a charge storage film, and a blocking insulation film. The example embodiment may also include field isolation films, which partially fill the trenches of the semiconductor substrate, such that the upper surfaces of the active regions or the substrate are higher than the upper surfaces of the field isolation films.

摘要翻译： 在示例性实施例中，半导体衬底具有由多个沟槽分隔开的多个有源区域。 栅极绝缘膜填充沟槽的至少一部分，并且在栅极绝缘膜上形成导电栅极膜。 在示例性实施例中，栅极绝缘膜可以包括隧道绝缘膜，电荷存储膜和阻挡绝缘膜。 示例实施例还可以包括场隔离膜，其部分地填充半导体衬底的沟槽，使得有源区或衬底的上表面高于场隔离膜的上表面。

公开(公告)号：US06995424B2

公开(公告)日：2006-02-07

申请号：US10712426

申请日：2003-11-13

申请人： Chang-Hyun Lee

发明人： Chang-Hyun Lee

IPC分类号： H01L29/792

CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11573 ,  H01L29/66833

摘要： A non-volatile memory device comprises a cell region defined at a substrate and a plurality of device isolation layers formed in the cell region to define a plurality of active regions. A charge storage insulator covers substantially the entire top surface of the cell region. A plurality of gate lines are formed on the charge storage insulator that cross over the device isolation layers. Conductive patterns are disposed between predetermined gate lines that penetrate the charge storage insulator to electrically connect with the active regions. According to the method of fabricating the device, a plurality of device isolation layers are formed in the substrate and then a charge storage insulator is formed on an entire surface of the substrate and the device isolation layers. A plurality of parallel gate lines that cross over the device isolation layers are formed on the charge storage insulator and then conductive patterns are formed between predetermined gate lines. The conductive patterns penetrate the charge storage insulator and electrically connect with the active regions.

摘要翻译： 非易失性存储器件包括限定在衬底处的单元区域和形成在单元区域中以限定多个有源区域的多个器件隔离层。 电荷存储绝缘体基本上覆盖电池区域的整个顶表面。 在电荷存储绝缘体上形成有跨越器件隔离层的多条栅极线。 导电图案设置在穿过电荷存储绝缘体的预定栅极线之间以与有源区电连接。 根据该器件的制造方法，在衬底中形成多个器件隔离层，然后在衬底和器件隔离层的整个表面上形成电荷存储绝缘体。 在电荷存储绝缘体上形成跨越器件隔离层的多条平行栅极线，然后在预定栅极线之间形成导电图案。 导电图案穿透电荷存储绝缘体并与有源区电连接。

公开(公告)号：US06987694B2

公开(公告)日：2006-01-17

申请号：US10640082

申请日：2003-08-13

申请人： Chang-Hyun Lee

发明人： Chang-Hyun Lee

IPC分类号： G11C16/00

CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/3418

摘要： A non-volatile memory device may include a string of serially connected memory cell transistors with each memory cell transistor of the string being connected to a different word line. The non-volatile memory device may be programmed by applying a pass voltage to a first word line connected to a first memory cell transistor of the string, by applying a coupling voltage to a second word line connected to a second memory cell transistor of the string, and by applying a program voltage to a third word line connected to a third memory cell transistor of the string. More particularly, the coupling voltage can be greater than a ground voltage of the memory device, and the pass voltage and the coupling voltage can be different. In addition, the program voltage can be applied to the third word line while applying the pass voltage to the first word line and while applying the coupling voltage to the second word line, and the third memory cell transistor can be programmed responsive to applying the program voltage to the third word line wherein the second memory cell transistor is between the first and third memory cell transistors of the serially connected string. Related devices are also discussed.

摘要翻译： 非易失性存储器件可以包括一串串联的存储单元晶体管，其中串的每个存储单元晶体管连接到不同的字线。 可以通过向连接到串的第一存储单元晶体管的第一字线施加通过电压来对非易失性存储器件进行编程，通过向连接到串的第二存储单元晶体管的第二字线施加耦合电压 并且通过对连接到串的第三存储单元晶体管的第三字线施加编程电压。 更具体地，耦合电压可以大于存储器件的接地电压，并且通过电压和耦合电压可以不同。 此外，可以将编程电压施加到第三字线，同时将通过电压施加到第一字线，同时将耦合电压施加到第二字线，并且第三存储单元晶体管可以响应于应用程序而被编程 电压到第三字线，其中第二存储单元晶体管位于串行连接的串的第一和第三存储单元晶体管之间。 还讨论了相关设备。

公开(公告)号：US06947330B2

公开(公告)日：2005-09-20

申请号：US10401372

申请日：2003-03-28

申请人： Chang-Hyun Lee

发明人： Chang-Hyun Lee

IPC分类号： H01L27/115 ,  G11C16/04 ,  G11C16/14 ,  H01L29/792

CPC分类号： G11C16/0466 ,  G11C16/04 ,  G11C16/10 ,  G11C16/14 ,  G11C16/349 ,  G11C29/50 ,  G11C29/50004

摘要： An electrically erasable charge trap nonvolatile memory cell has an initial threshold voltage, a program voltage that is higher than the initial threshold voltage, and an erase threshold voltage that is lower than the program threshold voltage but is higher than the initial threshold voltage. The programmed electrically erasable charge trap nonvolatile memory cells may be erased by applying an erase voltage for a time interval that is sufficient to lower the threshold voltage the transistor from a program threshold voltage to an erase threshold voltage that is lower than the program threshold voltage, but is higher than the initial threshold voltage. The time interval may be determined by repeatedly performing an endurance test using a time interval that is increased or decreased from an initial time interval, to obtain the time interval that meets an endurance specification, or allows a read to be performed successfully.

摘要翻译： 电可擦除电荷陷阱非易失性存储单元具有初始阈值电压，高于初始阈值电压的编程电压和低于编程阈值电压但高于初始阈值电压的擦除阈值电压。 可以通过施加足以将晶体管的阈值电压从编程阈值电压降低到低于编程阈值电压的擦除阈值电压的时间间隔施加擦除电压来擦除编程的电可擦除电荷陷阱非易失性存储器单元， 但高于初始阈值电压。 可以通过使用从初始时间间隔增加或减少的时间间隔重复执行耐久性测试来获得时间间隔，以获得满足耐久性规范的时间间隔，或允许成功执行读取。