中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

22 records (took 0.02 seconds)

    METHOD OF FABRICATING CELL OF NONVOLATILE MEMORY DEVICE WITH FLOATING GATE
    1.
    发明申请
    METHOD OF FABRICATING CELL OF NONVOLATILE MEMORY DEVICE WITH FLOATING GATE 有权
    具有浮动门的非易失性存储器件的制造方法

    公开(公告)号：US20070029603A1

    公开(公告)日：2007-02-08

    申请号：US11530827

    申请日：2006-09-11

    Applicant: Chang-Hyun LEE ,  Kyu-Charn PARK ,  Jeong-Hyuk CHOI ,  Sung-Hoi HUR

    Inventor： Chang-Hyun LEE ,  Kyu-Charn PARK ,  Jeong-Hyuk CHOI ,  Sung-Hoi HUR

    IPC: H01L29/788 ,  H01L29/792

    CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L27/11519 ,  Y10S257/905

    Abstract: This disclosure provides cells of nonvolatile memory devices with floating gates and methods for fabricating the same. The cell of the nonvolatile memory device includes device isolation layers in parallel with each other on a predetermined region of a semiconductor substrate that define a plurality of active regions. Each device isolation layer has sidewalls that project over the semiconductor substrate. A plurality of word lines crosses over the device isolation layers. A tunnel oxide layer, a floating gate, a gate interlayer dielectric layer, and a control gate electrode are sequentially stacked between each active region and each word line. The floating gate and the control gate electrode have sidewalls that are self-aligned to the adjacent device isolation layers. The method for forming the self-aligned floating gate and the control gate electrode includes forming trenches in a semiconductor substrate to define a plurality of active regions and concurrently forming an oxide layer pattern, a floating gate pattern, a dielectric layer pattern and a control gate pattern that are sequentially stacked. A conductive layer is then formed on the device isolation layers and the control gate pattern. Thereafter, the conductive layer, the control gate pattern, the dielectric layer pattern, the floating gate pattern, and the oxide layer pattern are successively patterned.

    Abstract translation: 本公开提供具有浮动栅极的非易失性存储器件单元以及用于制造其的方法。 非易失性存储器件的单元包括在限定多个有源区域的半导体衬底的预定区域上彼此并联的器件隔离层。 每个器件隔离层具有突出在半导体衬底上的侧壁。 多个字线跨越器件隔离层。 隧道氧化物层，浮置栅极，栅极层间电介质层和控制栅极电极顺序堆叠在每个有源区域和每条字线之间。 浮栅和控制栅极具有与相邻器件隔离层自对准的侧壁。 形成自对准浮栅和控制栅极的方法包括在半导体衬底中形成沟槽以限定多个有源区并同时形成氧化物层图案，浮栅图案，电介质层图案和控制栅极 顺序堆叠的图案。 然后在器件隔离层和控制栅极图案上形成导电层。 此后，连续地形成导电层，控制栅极图案，电介质层图案，浮栅图案和氧化物层图案。

    SEMICONDUCTOR DEVICE CAPABLE OF SUPPRESSING SHORT CHANNEL EFFECT
    2.
    发明申请
    SEMICONDUCTOR DEVICE CAPABLE OF SUPPRESSING SHORT CHANNEL EFFECT 有权
    能够抑制短路通道效应的半导体器件

    公开(公告)号：US20120007168A1

    公开(公告)日：2012-01-12

    申请号：US13239504

    申请日：2011-09-22

    Applicant: Chang-Hyun LEE ,  Jung-Dal Choi

    Inventor： Chang-Hyun LEE ,  Jung-Dal Choi

    IPC: H01L29/78

    CPC classification number: H01L27/11521 ,  H01L21/26586 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/1083

    Abstract: A semiconductor device includes a semiconductor substrate including at least one memory channel region and at least one memory source/drain region, the memory channel region and the memory source/drain region being arranged alternately, and at least one word line on the memory channel region, wherein the memory source/drain region has a higher net impurity concentration than the memory channel region.

    Abstract translation: 半导体器件包括半导体衬底，该半导体衬底包括至少一个存储器沟道区和至少一个存储源/漏区，存储器沟道区和存储源/漏区被交替排列，以及存储器沟道区上的至少一个字线 其中，所述存储器源极/漏极区域具有比所述存储器沟道区域更高的净杂质浓度。

    NAND FLASH MEMORY DEVICE AND METHODS OF ITS FORMATION AND OPERATION
    5.
    发明申请
    NAND FLASH MEMORY DEVICE AND METHODS OF ITS FORMATION AND OPERATION 有权
    NAND闪存存储器件及其形成和操作方法

    公开(公告)号：US20080002471A1

    公开(公告)日：2008-01-03

    申请号：US11852919

    申请日：2007-09-10

    Applicant: Chang-Hyun LEE

    Inventor： Chang-Hyun LEE

    IPC: G11C11/34

    CPC classification number: G11C16/0483 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

    Abstract: A NAND flash memory device, and methods of forming and operating the same are provided. The NAND flash memory device includes first and second selection gate lines sequentially disposed at one side of a plurality of cell gate lines. A first selection transistor including the first selection gate line serves as a buffer for decreasing a highly boosted channel voltage of a non-selected cell to minimize the leakage current of the NAND flash memory device.

    Abstract translation: 提供了一种NAND闪速存储器件及其形成和操作方法。 NAND闪存器件包括顺序地设置在多个单元栅极线的一侧的第一和第二选择栅极线。 包括第一选择栅极线的第一选择晶体管用作用于降低非选择单元的高度提升的沟道电压的缓冲器，以使NAND闪速存储器件的漏电流最小化。

    VERTICAL MEMORY DEVICES
    7.
    发明申请
    VERTICAL MEMORY DEVICES 审中-公开

    公开(公告)号：US20170256564A1

    公开(公告)日：2017-09-07

    申请号：US15455900

    申请日：2017-03-10

    Applicant: Chang-Hyun LEE

    Inventor： Chang-Hyun LEE

    IPC: H01L27/11582 ,  H01L29/792 ,  H01L29/66 ,  H01L29/04 ,  H01L29/16

    CPC classification number: H01L27/11582 ,  H01L29/04 ,  H01L29/16 ,  H01L29/66833 ,  H01L29/7926

    Abstract: According to example embodiments, a vertical memory device includes a low resistance layer on a lower insulation layer, a channel layer on the low resistance layer, a plurality of vertical channels on the channel layer, and a plurality of gate lines. The vertical channels extend in a first direction that is perpendicular with respect to a top surface of the channel layer. The gate lines surround outer sidewalls of the vertical channels, and are stacked in the first direction and are spaced apart from each other.

    METHOD OF OPERATING NONVOLATILE MEMORY DEVICE
    8.
    发明申请
    METHOD OF OPERATING NONVOLATILE MEMORY DEVICE 审中-公开
    操作非易失性存储器件的方法

    公开(公告)号：US20150146489A1

    公开(公告)日：2015-05-28

    申请号：US14477513

    申请日：2014-09-04

    Applicant: Chang-Hyun LEE ,  Albert FAYRUSHIN

    Inventor： Chang-Hyun LEE ,  Albert FAYRUSHIN

    IPC: G11C16/14 ,  G11C16/34

    CPC classification number: G11C16/14 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/16 ,  G11C16/3459 ,  H01L27/11582

    Abstract: In a method of operating a nonvolatile memory device having a substrate and first through n-th word lines stacked in a direction perpendicular to the substrate, first through k-th word line voltages are applied to first through k-th word lines, respectively, which are formed adjacent to the substrate, among the first through n-th word lines. (k+1)-th through n-th word line voltages are applied to (k+1)-th through n-th word lines, respectively, which are formed above the first through k-th word lines, among the first through n-th word lines. An erase voltage, which is higher than the first through n-th word line voltages, is applied to the substrate, where n represents an integer equal to or greater than two, and k represents a positive integer smaller than n. Each of the (k+1)-th through n-th word line voltages is lower than each of the first through k-th word line voltages.

    Abstract translation: 在具有基板和在与基板垂直的方向上堆叠的第一至第n字线的非易失性存储器件的操作方法中，第一至第k字线电压分别施加到第一至第k字线， 在第一至第n字线之间形成与基板相邻的第一至第n字线。 第（k + 1）〜第n字线电压分别施加到形成在第一至第k字线之上的第（k + 1）至第n字线， 第n个字线。 将高于第一至第n字线电压的擦除电压施加到衬底，其中n表示等于或大于2的整数，并且k表示小于n的正整数。 第（k + 1）至第n字线电压中的每一个低于第一至第k字线电压中的每一个。

    Non-Volatile Memory Devices
    9.
    发明申请
    Non-Volatile Memory Devices 审中-公开
    非易失性存储器件

    公开(公告)号：US20120132982A1

    公开(公告)日：2012-05-31

    申请号：US13282575

    申请日：2011-10-27

    Applicant: Chang-Hyun LEE ,  Byung-Kyu CHO ,  Jang-Hyun YOU ,  Albert FAYRUSHIN

    Inventor： Chang-Hyun LEE ,  Byung-Kyu CHO ,  Jang-Hyun YOU ,  Albert FAYRUSHIN

    IPC: H01L29/788

    CPC classification number: H01L29/42364 ,  H01L21/02109 ,  H01L21/02304 ,  H01L21/764 ,  H01L21/7682 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/40114 ,  H01L29/42324 ,  H01L29/66825

    Abstract: A non-volatile memory device includes gate structures, an insulation layer pattern, and an isolation structure. Multiple gate structures being spaced apart from each other in a first direction are formed on a substrate. Ones of the gate structures extend in a second direction that is substantially perpendicular to the first direction. The substrate includes active regions and field regions alternately and repeatedly formed in the second direction. The insulation layer pattern is formed between the gate structures and has a second air gap therein. Each of the isolation structures extending in the first direction and having a first air gap between the gate structures, the insulation layer pattern, and the isolation structure is formed on the substrate in each field region.

    Abstract translation: 非易失性存储器件包括栅极结构，绝缘层图案和隔离结构。 在第一方向上彼此间隔开的多个栅极结构形成在基板上。 栅极结构的一部分在基本上垂直于第一方向的第二方向上延伸。 衬底包括在第二方向上交替且重复地形成的有源区和场区。 绝缘层图案形成在栅极结构之间并且其中具有第二气隙。 在每个场区域的基板上形成有在第一方向上延伸并且在栅极结构之间具有第一空气间隙，绝缘层图案和隔离结构的隔离结构。

Patent Agency Ranking