公开(公告)号：US08610421B2

公开(公告)日：2013-12-17

申请号：US12976504

申请日：2010-12-22

Applicant: Ming-Chieh Huang ,  Chan-Hong Chern ,  Chih-Chang Lin

Inventor： Ming-Chieh Huang ,  Chan-Hong Chern ,  Chih-Chang Lin

IPC: G05F1/648

CPC classification number: G05F1/648 ,  G11C5/147 ,  H02M3/158

Abstract: A current generator includes an op-amp having a negative terminal arranged to be coupled to an input voltage, a resistance selection circuit having at least one tunable resistor connected with each other, and at least one power transistor. A gate of the at least one power transistor is coupled to an output of the op-amp, and a drain of the at least one power transistor is coupled to the at least one tunable resistor or a load. The resistance selection circuit is configured to select a node of the at least one tunable resistor based on the input voltage for coupling from a positive terminal of the op-amp. The at least one tunable resistor is configured to adjust a resistance setting to control a current level of the current generator based on a power supply voltage or a current of a reference resistor.

Abstract translation: 电流发生器包括具有布置为耦合到输入电压的负极端子的运算放大器，具有彼此连接的至少一个可调电阻器的电阻选择电路和至少一个功率晶体管。 所述至少一个功率晶体管的栅极耦合到所述运算放大器的输出，并且所述至少一个功率晶体管的漏极耦合到所述至少一个可调电阻器或负载。 电阻选择电路被配置为基于用于从运算放大器的正极端子耦合的输入电压来选择至少一个可调电阻器的节点。 所述至少一个可调电阻器被配置为基于电源电压或参考电阻器的电流来调整电阻设置以控制电流发生器的电流水平。

公开(公告)号：US20130121396A1

公开(公告)日：2013-05-16

申请号：US13293513

申请日：2011-11-10

Applicant: Ming-Chieh HUANG ,  Jing Jing CHEN ,  Chan-Hong CHERN ,  Tao Wen CHUNG ,  Chih-Chang LIN ,  Yuwen SWEI

Inventor： Ming-Chieh HUANG ,  Jing Jing CHEN ,  Chan-Hong CHERN ,  Tao Wen CHUNG ,  Chih-Chang LIN ,  Yuwen SWEI

IPC: H04L27/01

CPC classification number: H04L25/03057 ,  H04L2025/0349 ,  H04L2025/03566 ,  H04L2025/03617 ,  H04L2025/03687

Abstract: A Decision Feedback Equalizer (DFE) with programmable taps includes a summer configured to receive a DFE input signal. Delay elements are coupled to the summer. The delay elements are connected in series. Each delay element provides a respective delayed signal of an input signal to the delay element. A weight generator is configured to provide tap weights. The DFE is configured to multiply each tap weight to the respective delayed signal from the respective delay element to provide tap outputs. Each tap output is selectively enabled to be added to the summer or disabled based on a first comparison of a first threshold value and each impulse response or each tap weight corresponding to the respective tap output, where the impulse response is the DFE input signal in response to a pulse signal transmitted through a channel.

Abstract translation: 具有可编程抽头的判决反馈均衡器（DFE）包括一个加法器，用于接收DFE输入信号。 延迟元素与夏天相结合。 延迟元件串联连接。 每个延迟元件向延迟元件提供输入信号的相应延迟信号。 重量发生器被配置成提供抽头重量。 DFE被配置为将每个抽头权重乘以来自相应延迟元件的相应延迟信号以提供抽头输出。 基于第一阈值和对应于各抽头输出的每个脉冲响应或每个抽头权重的第一比较，每个抽头输出被选择性地被加到加法器或禁止中，其中脉冲响应是响应中的DFE输入信号 通过通道传输的脉冲信号。

公开(公告)号：US20130106475A1

公开(公告)日：2013-05-02

申请号：US13718235

申请日：2012-12-18

Applicant: Chih-Chang LIN ,  Chan-Hong CHERN ,  Steven SWEI ,  Ming-Chieh HUANG ,  Tien-Chun YANG

Inventor： Chih-Chang LIN ,  Chan-Hong CHERN ,  Steven SWEI ,  Ming-Chieh HUANG ,  Tien-Chun YANG

IPC: H03L7/08

CPC classification number: H03L7/08 ,  H03L7/081 ,  H03L7/087

Abstract: A method of operating a charge pump of a phase-lock assistant circuit includes determining a first relative timing relationship of a phase of a data signal to a phase of a first phase clock. A second relative timing relationship of the phase of the data signal to a phase of a second phase clock is determined, and the first and second phase clocks have a 45° phase difference. An up signal and a down signal are generated in response to the first relative timing relationship and the second relative timing relationship. The charge pump circuit is driven according to the up signal and the down signal.

Abstract translation: 操作锁相辅助电路的电荷泵的方法包括确定数据信号的相位与第一相位时钟的相位的第一相对定时关系。 确定数据信号的相位与第二相位时钟的相位的第二相对定时关系，并且第一和第二相位时钟具有45°的相位差。 响应于第一相对定时关系和第二相对定时关系产生升高信号和下降信号。 电荷泵电路根据上升信号和下降信号进行驱动。

公开(公告)号：US20130082754A1

公开(公告)日：2013-04-04

申请号：US13252498

申请日：2011-10-04

Applicant: Chan-Hong CHERN ,  Ming-Chieh HUANG ,  Tao Wen CHUNG ,  Chih-Chang LIN ,  Fu-Lung HSUEH ,  Yuwen SWEI

Inventor： Chan-Hong CHERN ,  Ming-Chieh HUANG ,  Tao Wen CHUNG ,  Chih-Chang LIN ,  Fu-Lung HSUEH ,  Yuwen SWEI

IPC: H03L7/08

CPC classification number: H03L7/102 ,  H03L7/099 ,  H03L2207/06

Abstract: An inductor-capacitor phase locked loop (LCPLL) includes an inductor-capacitor voltage controlled oscillator (LCVCO) that provides an output frequency. A calibration circuit includes two comparators and provides a coarse tune signal to the LCVCO. The two comparators respectively compare the loop filter signal with a first reference voltage and a second reference voltage that is higher than the first reference voltage to supply a first and second comparator output, respectively. The calibration circuit is capable of adjusting the coarse tune signal continuously in voltage values and adjusts the coarse tune signal based on the two comparator outputs. A loop filter provides a loop filter signal to the calibration circuit and a fine tune signal to the LCVCO. A coarse tune frequency range is greater than a fine tune frequency range.

Abstract translation: 电感 - 电容器锁相环（LCPLL）包括提供输出频率的电感 - 电容压控振荡器（LCVCO）。 校准电路包括两个比较器，并向LCVCO提供粗调信号。 两个比较器分别将环路滤波器信号与第一参考电压和高于第一参考电压的第二参考电压进行比较，以分别提供第一和第二比较器输出。 校准电路能够在电压值中连续调整粗调信号，并根据两个比较器输出调整粗调信号。 环路滤波器向校准电路提供环路滤波器信号，并向LCVCO提供微调信号。 粗调频率范围大于微调频率范围。

公开(公告)号：US20120161742A1

公开(公告)日：2012-06-28

申请号：US12976504

申请日：2010-12-22

Applicant: Ming-Chieh HUANG ,  Chan-Hong CHERN ,  Chih-Chang LIN

Inventor： Ming-Chieh HUANG ,  Chan-Hong CHERN ,  Chih-Chang LIN

IPC: G05F5/08

CPC classification number: G05F1/648 ,  G11C5/147 ,  H02M3/158

Abstract: A current generator includes an op-amp having a negative terminal arranged to be coupled to an input voltage, a resistance selection circuit having at least one tunable resistor connected with each other, and at least one power transistor. A gate of the at least one power transistor is coupled to an output of the op-amp, and a drain of the at least one power transistor is coupled to the at least one tunable resistor or a load. The resistance selection circuit is configured to select a node of the at least one tunable resistor based on the input voltage for coupling from a positive terminal of the op-amp. The at least one tunable resistor is configured to adjust a resistance setting to control a current level of the current generator based on a power supply voltage or a current of a reference resistor.

Abstract translation: 电流发生器包括具有布置为耦合到输入电压的负极端子的运算放大器，具有彼此连接的至少一个可调电阻器的电阻选择电路和至少一个功率晶体管。 所述至少一个功率晶体管的栅极耦合到所述运算放大器的输出，并且所述至少一个功率晶体管的漏极耦合到所述至少一个可调电阻器或负载。 电阻选择电路被配置为基于用于从运算放大器的正极端子耦合的输入电压来选择至少一个可调电阻器的节点。 所述至少一个可调电阻器被配置为基于电源电压或参考电阻器的电流来调整电阻设置以控制电流发生器的电流水平。

公开(公告)号：US08207775B2

公开(公告)日：2012-06-26

申请号：US12871343

申请日：2010-08-30

Applicant: Chan-Hong Chern ,  Fu-Lung Hsueh ,  Yuwen Swei ,  Chih-Chang Lin

Inventor： Chan-Hong Chern ,  Fu-Lung Hsueh ,  Yuwen Swei ,  Chih-Chang Lin

IPC: H03L5/00

CPC classification number: H03K19/0941 ,  H03K3/356182 ,  H03K19/018514

Abstract: A representative level-shifter comprises a dynamically biased current source circuit that receives a first voltage, a first and a second unidirectional current-conducting devices, a first and a second pull-down devices, and a pull-up device. The first and second unidirectional current-conducting devices are coupled to the dynamically biased current source circuit. A voltage output of the level-shifter is located at a first node that is located between the current-constant circuit and the second unidirectional current-conducting device. The first and second pull-down devices are coupled to the first and second unidirectional current-conducting devices, respectively. The pull-up device receives a second voltage and is coupled to the dynamically biased current source circuit and the first unidirectional current-conducting device. The pull-up device is configured to dynamically bias the dynamically biased current source circuit such that a voltage drop of the second unidirectional current-conducting device is output at the voltage output responsive to the pull-up device outputting the second voltage to the dynamically biased current source circuit, the first pull-down device being non-conducting and the second pull-down device being conducting.

Abstract translation: 代表性的电平转换器包括接收第一电压，第一和第二单向导流器件，第一和第二下拉器件以及上拉器件的动态偏置电流源电路。 第一和第二单向导流器件耦合到动态偏置电流源电路。 电平移位器的电压输出位于位于电流恒定电路和第二单向导流器件之间的第一节点处。 第一和第二下拉装置分别耦合到第一和第二单向导流装置。 上拉装置接收第二电压并耦合到动态偏置电流源电路和第一单向导流装置。 上拉装置被配置为动态地偏置动态偏置的电流源电路，使得第二单向导流装置的电压降在电压输出处被输出，响应于上拉装置将第二电压输出到动态偏置 电流源电路，第一下拉装置不导通，第二下拉装置导通。

公开(公告)号：US08183913B2

公开(公告)日：2012-05-22

申请号：US12706886

申请日：2010-02-17

Applicant: Steven Swei ,  Chih-Chang Lin ,  Tien-Chun Yang ,  Chan-Hong Chern ,  Ming-Chieh Huang

Inventor： Steven Swei ,  Chih-Chang Lin ,  Tien-Chun Yang ,  Chan-Hong Chern ,  Ming-Chieh Huang

IPC: G05F1/10 ,  G05F3/02

CPC classification number: G05F1/10 ,  G05F3/02 ,  H03L7/0895 ,  H03L7/0896 ,  H03L7/0898

Abstract: An integrated circuit includes a first current source. A second current source is electrically coupled with the first current source via a conductive line. A switch circuit is coupled between the first current source and the second current source. A first circuit is coupled between a first node and a second node. The first node is disposed between the first current source and the switch circuit. The second node is coupled with the first current source. The first circuit is configured for substantially equalizing voltages on the first node and the second node. A second circuit is coupled between a third node and a fourth node. The third node is disposed between the second current source and the switch circuit. The fourth node is disposed coupled with the second current source. The second circuit is configured for substantially equalizing voltages on the third node and the fourth node.

Abstract translation: 集成电路包括第一电流源。 第二电流源经由导线与第一电流源电耦合。 开关电路耦合在第一电流源和第二电流源之间。 第一电路耦合在第一节点和第二节点之间。 第一节点设置在第一电流源和开关电路之间。 第二节点与第一电流源耦合。 第一电路被配置为基本上均衡第一节点和第二节点上的电压。 第二电路耦合在第三节点和第四节点之间。 第三节点设置在第二电流源和开关电路之间。 第四节点被布置成与第二电流源耦合。 第二电路被配置为基本上均衡第三节点和第四节点上的电压。

公开(公告)号：US20120050930A1

公开(公告)日：2012-03-01

申请号：US12871343

申请日：2010-08-30

Applicant: Chan-Hong CHERN ,  Fu-Lung HSUEH ,  Yuwen SWEI ,  Chih-Chang LIN

Inventor： Chan-Hong CHERN ,  Fu-Lung HSUEH ,  Yuwen SWEI ,  Chih-Chang LIN

IPC: H02H9/04 ,  H03L5/00

CPC classification number: H03K19/0941 ,  H03K3/356182 ,  H03K19/018514

Abstract: A representative level-shifter comprises a dynamically biased current source circuit that receives a first voltage, a first and a second unidirectional current-conducting devices, a first and a second pull-down devices, and a pull-up device. The first and second unidirectional current-conducting devices are coupled to the dynamically biased current source circuit. A voltage output of the level-shifter is located at a first node that is located between the current-constant circuit and the second unidirectional current-conducting device. The first and second pull-down devices are coupled to the first and second unidirectional current-conducting devices, respectively. The pull-up device receives a second voltage and is coupled to the dynamically biased current source circuit and the first unidirectional current-conducting device. The pull-up device is configured to dynamically bias the dynamically biased current source circuit such that a voltage drop of the second unidirectional current-conducting device is output at the voltage output responsive to the pull-up device outputting the second voltage to the dynamically biased current source circuit, the first pull-down device being non-conducting and the second pull-down device being conducting.

Abstract translation: 代表性的电平转换器包括接收第一电压，第一和第二单向导流器件，第一和第二下拉器件以及上拉器件的动态偏置电流源电路。 第一和第二单向导流器件耦合到动态偏置电流源电路。 电平移位器的电压输出位于位于电流恒定电路和第二单向导流器件之间的第一节点处。 第一和第二下拉装置分别耦合到第一和第二单向导流装置。 上拉装置接收第二电压并耦合到动态偏置电流源电路和第一单向导流装置。 上拉装置被配置为动态地偏置动态偏置的电流源电路，使得第二单向导流装置的电压降在电压输出处被输出，响应于上拉装置将第二电压输出到动态偏置 电流源电路，第一下拉装置不导通，第二下拉装置导通。

公开(公告)号：US20110310690A1

公开(公告)日：2011-12-22

申请号：US12820712

申请日：2010-06-22

Applicant: Ming-Chieh HUANG ,  Chan-Hong CHERN ,  Tien Chun YANG ,  Chih-Chang LIN ,  Yuwen SWEI

Inventor： Ming-Chieh HUANG ,  Chan-Hong CHERN ,  Tien Chun YANG ,  Chih-Chang LIN ,  Yuwen SWEI

IPC: G11C5/14

CPC classification number: G11C11/4074 ,  G11C5/147

Abstract: A voltage regulator includes an output stage electrically coupled with an output end of the voltage regulator. The output stage includes at least one transistor having a bulk and a drain. At least one back-bias circuit is electrically coupled with the bulk of the at least one transistor. The at least one back-bias circuit is configured to provide a bulk voltage, such that the bulk and the drain of the at least one transistor are reverse biased during a standby mode of a memory array that is electrically coupled with the voltage regulator.

Abstract translation: 电压调节器包括与电压调节器的输出端电耦合的输出级。 输出级包括具有体积和漏极的至少一个晶体管。 至少一个背偏置电路与所述至少一个晶体管的主体电耦合。 至少一个背偏置电路被配置为提供体电压，使得在与电压调节器电耦合的存储器阵列的待机模式期间，至少一个晶体管的体积和漏极被反向偏置。

公开(公告)号：US20110267107A1

公开(公告)日：2011-11-03

申请号：US12768899

申请日：2010-04-28

Applicant: Chan-Hong CHERN ,  Fu-Lung HSUEH ,  Ming-Chieh HUANG ,  Bryan SHEFFIELD ,  Chih-Chang LIN

Inventor： Chan-Hong CHERN ,  Fu-Lung HSUEH ,  Ming-Chieh HUANG ,  Bryan SHEFFIELD ,  Chih-Chang LIN

IPC: H03K19/094 ,  H03K19/096

CPC classification number: H03K19/01855 ,  H03K3/012 ,  H03K3/356008 ,  H03K3/35625 ,  H03K19/0016 ,  H03K19/0963

Abstract: A circuit includes an operational PMOS transistor of a logic gate driver. A control circuit is configured to turn off the operational PMOS transistor during a standby mode. The circuit also includes a sacrificial PMOS transistor coupled to an output node. The operational PMOS transistor is coupled to the output node. The sacrificial PMOS transistor is configured to keep the output node at a logical 1 during the standby mode.

Abstract translation: 电路包括逻辑门驱动器的操作PMOS晶体管。 控制电路被配置为在待机模式期间关闭操作PMOS晶体管。 电路还包括耦合到输出节点的牺牲PMOS晶体管。 操作PMOS晶体管耦合到输出节点。 牺牲PMOS晶体管被配置为在待机模式期间将输出节点保持在逻辑1。