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公开(公告)号：US20110267107A1
公开(公告)日：2011-11-03
申请号：US12768899
申请日：2010-04-28
IPC分类号： H03K19/094 , H03K19/096
CPC分类号： H03K19/01855 , H03K3/012 , H03K3/356008 , H03K3/35625 , H03K19/0016 , H03K19/0963
摘要： A circuit includes an operational PMOS transistor of a logic gate driver. A control circuit is configured to turn off the operational PMOS transistor during a standby mode. The circuit also includes a sacrificial PMOS transistor coupled to an output node. The operational PMOS transistor is coupled to the output node. The sacrificial PMOS transistor is configured to keep the output node at a logical 1 during the standby mode.
摘要翻译： 电路包括逻辑门驱动器的操作PMOS晶体管。 控制电路被配置为在待机模式期间关闭操作PMOS晶体管。 电路还包括耦合到输出节点的牺牲PMOS晶体管。 操作PMOS晶体管耦合到输出节点。 牺牲PMOS晶体管被配置为在待机模式期间将输出节点保持在逻辑1。
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公开(公告)号：US20130342247A1
公开(公告)日：2013-12-26
申请号：US13530136
申请日：2012-06-22
申请人： Chan-Hong CHERN , Tao Wen CHUNG , Ming-Chieh HUANG , Chih-Chang LIN , Tsung-Ching HUANG , Fu-Lung HSUEH
发明人： Chan-Hong CHERN , Tao Wen CHUNG , Ming-Chieh HUANG , Chih-Chang LIN , Tsung-Ching HUANG , Fu-Lung HSUEH
IPC分类号： H03L7/08
CPC分类号： H03L7/103 , H03L7/097 , H03L7/0995 , H03L7/1072 , H03L7/18 , H03L2207/06
摘要： A circuit includes a capacitive-load voltage controlled oscillator having an input configured to receive a first input signal and an output configured to output an oscillating output signal. A calibration circuit is coupled to the voltage controlled oscillator and is configured to output one or more control signals to the capacitive-load voltage controlled oscillator for adjusting a frequency of the oscillating output signal. The calibration circuit is configured to output the one or more control signals in response to a comparison of an input voltage to at least one reference voltage.
摘要翻译： 电路包括电容负载压控振荡器，其具有被配置为接收第一输入信号的输入和被配置为输出振荡输出信号的输出。 校准电路耦合到压控振荡器，并被配置为将一个或多个控制信号输出到电容负载压控振荡器，用于调整振荡输出信号的频率。 校准电路被配置为响应于输入电压与至少一个参考电压的比较而输出一个或多个控制信号。
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3.发明申请CLOCK AND DATA RECOVERY USING LC VOLTAGE CONTROLLED OSCILLATOR AND DELAY LOCKED LOOP 有权使用LC电压控制振荡器和延迟锁定环路的时钟和数据恢复公开(公告)号：US20120230457A1
公开(公告)日：2012-09-13
申请号：US13045788
申请日：2011-03-11
IPC分类号： H04L7/00
CPC分类号： H04L7/033 , H03L7/0807 , H03L7/081 , H03L7/113 , H04L7/0337
摘要： A clock and data recovery (CDR) circuit includes an inductor-capacitor voltage controlled oscillator (LCVCO) configured to generate a clock signal with a clock frequency. A delay locked loop (DLL) is configured to receive the clock signal from the LCVCO and generate multiple clock phases. A charge pump is configured to control the LCVCO. A phase detector is configured to receive a data input and the multiple clock phases from the DLL, and to control the first charge pump in order to align a data edge of the data input and the multiple clock phases.
摘要翻译： 时钟和数据恢复（CDR）电路包括被配置为产生具有时钟频率的时钟信号的电感器 - 电容器压控振荡器（LCVCO）。 延迟锁定环（DLL）被配置为从LCVCO接收时钟信号并生成多个时钟相位。 电荷泵配置为控制LCVCO。 相位检测器被配置为从DLL接收数据输入和多个时钟相位，并且控制第一电荷泵以便对准数据输入和多个时钟相位的数据沿。
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公开(公告)号：US20120044008A1
公开(公告)日：2012-02-23
申请号：US12859456
申请日：2010-08-19
申请人： Chan-Hong CHERN , Fu-Lung HSUEH , Chih-Chang LIN , Yuwen SWEI , Ming-Chieh HUANG
发明人： Chan-Hong CHERN , Fu-Lung HSUEH , Chih-Chang LIN , Yuwen SWEI , Ming-Chieh HUANG
IPC分类号： H03L5/00
CPC分类号： H03K3/02 , H03K19/018521 , H03K19/018528
摘要： A level shifter includes an input node, an output node, a pull-up transistor, a pull-down transistor, and at least one diode-connected device coupled between the pull-up transistor and the pull-down transistor. The level shifter is arranged to be coupled to a high power supply voltage, to receive an input signal having a first voltage level at the input node, and to supply an output signal having a second voltage level at the output node. The high power supply voltage is higher than the first voltage level. The at least one diode-connected device allows the output signal to be pulled up to about a first diode voltage drop below the high power supply voltage and/or to be pulled down to about a second diode voltage drop above ground. The first diode voltage drop and the second diode voltage drop are from the at least one diode-connected device.
摘要翻译： 电平移位器包括输入节点，输出节点，上拉晶体管，下拉晶体管以及耦合在上拉晶体管和下拉晶体管之间的至少一个二极管连接器件。 电平移位器被布置为耦合到高电源电压，以在输入节点处接收具有第一电压电平的输入信号，并且在输出节点处提供具有第二电压电平的输出信号。 高电源电压高于第一电压电平。 所述至少一个二极管连接的装置允许输出信号被上拉到大约低于高电源电压的第一二极管电压降和/或被下拉到大约地面上的第二二极管电压降。 第一二极管电压降和第二二极管压降来自至少一个二极管连接的器件。
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公开(公告)号：US20130082754A1
公开(公告)日：2013-04-04
申请号：US13252498
申请日：2011-10-04
申请人： Chan-Hong CHERN , Ming-Chieh HUANG , Tao Wen CHUNG , Chih-Chang LIN , Fu-Lung HSUEH , Yuwen SWEI
发明人： Chan-Hong CHERN , Ming-Chieh HUANG , Tao Wen CHUNG , Chih-Chang LIN , Fu-Lung HSUEH , Yuwen SWEI
IPC分类号： H03L7/08
CPC分类号： H03L7/102 , H03L7/099 , H03L2207/06
摘要： An inductor-capacitor phase locked loop (LCPLL) includes an inductor-capacitor voltage controlled oscillator (LCVCO) that provides an output frequency. A calibration circuit includes two comparators and provides a coarse tune signal to the LCVCO. The two comparators respectively compare the loop filter signal with a first reference voltage and a second reference voltage that is higher than the first reference voltage to supply a first and second comparator output, respectively. The calibration circuit is capable of adjusting the coarse tune signal continuously in voltage values and adjusts the coarse tune signal based on the two comparator outputs. A loop filter provides a loop filter signal to the calibration circuit and a fine tune signal to the LCVCO. A coarse tune frequency range is greater than a fine tune frequency range.
摘要翻译： 电感 - 电容器锁相环（LCPLL）包括提供输出频率的电感 - 电容压控振荡器（LCVCO）。 校准电路包括两个比较器，并向LCVCO提供粗调信号。 两个比较器分别将环路滤波器信号与第一参考电压和高于第一参考电压的第二参考电压进行比较，以分别提供第一和第二比较器输出。 校准电路能够在电压值中连续调整粗调信号，并根据两个比较器输出调整粗调信号。 环路滤波器向校准电路提供环路滤波器信号，并向LCVCO提供微调信号。 粗调频率范围大于微调频率范围。
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公开(公告)号：US20120019302A1
公开(公告)日：2012-01-26
申请号：US12843479
申请日：2010-07-26
IPC分类号： H03L5/00
CPC分类号： H03K19/018521
摘要： A level shifter includes one PMOS and two NMOS transistors. A source of the first NMOS transistor is coupled to a low power supply voltage. An input signal is coupled to a gate of the first NMOS transistor and a source of the second NMOS transistor. The input signal has a voltage level up to a first power supply voltage. A source of the PMOS transistor is coupled to a second power supply voltage, higher than the first power supply voltage. An output signal is coupled between the PMOS and the first NMOS transistors. The first NMOS transistor is arranged to pull down the output signal when the input signal is a logical 1, and the second NMOS transistor is arranged to enable the PMOS transistor to pull up the output signal to a logical 1 at the second power supply voltage when the input signal is a logical 0.
摘要翻译： 电平移位器包括一个PMOS和两个NMOS晶体管。 第一NMOS晶体管的源极耦合到低电源电压。 输入信号耦合到第一NMOS晶体管的栅极和第二NMOS晶体管的源极。 输入信号具有高达第一电源电压的电压电平。 PMOS晶体管的源极耦合到高于第一电源电压的第二电源电压。 输出信号耦合在PMOS和第一NMOS晶体管之间。 第一NMOS晶体管被布置为当输入信号为逻辑1时下拉输出信号，并且第二NMOS晶体管被布置为使得PMOS晶体管能够以第二电源电压将输出信号上拉至逻辑1， 输入信号为逻辑0。
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公开(公告)号：US20160087817A1
公开(公告)日：2016-03-24
申请号：US14492237
申请日：2014-09-22
申请人： Ming-Chieh HUANG , Chan-Hong CHERN , Tao Wen CHUNG , Yuwen SWEI , Chih-Chang LIN , Tsung-Ching HUANG
发明人： Ming-Chieh HUANG , Chan-Hong CHERN , Tao Wen CHUNG , Yuwen SWEI , Chih-Chang LIN , Tsung-Ching HUANG
CPC分类号： H04L25/03057 , H04L25/06 , H04L25/08
摘要： A circuit includes a summation circuit for receiving an input data signal and a feedback signal including a previous data bit. The summation circuit is configured to output a conditioned input data signal to a clock and data recovery circuit. A first flip-flop is coupled to an output of the summation circuit and is configured to receive a first set of bits of the conditioned input data signal and a first clock signal having a frequency that is less than a frequency at which the input data signal is received by the first summation circuit. A second flip-flop is coupled to the output of the summation circuit and is configured to receive a second set of bits of the conditioned input data signal and a second clock signal having a frequency that is less than the frequency at which the input data signal is received by the first summation circuit.
摘要翻译： 电路包括用于接收输入数据信号和包括先前数据位的反馈信号的求和电路。 求和电路被配置为将调节的输入数据信号输出到时钟和数据恢复电路。 第一触发器耦合到求和电路的输出，并且被配置为接收经调节的输入数据信号的第一比特组和具有小于输入数据信号的频率的频率的第一时钟信号 由第一求和电路接收。 第二触发器耦合到求和电路的输出，并且被配置为接收经调节的输入数据信号的第二组比特和具有小于输入数据信号的频率的频率的第二时钟信号 由第一求和电路接收。
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8.发明申请PHASE INTERPOLATOR FOR CLOCK DATA RECOVERY CIRCUIT WITH ACTIVE WAVE SHAPING INTEGRATORS 有权用于具有主动波形整合器的时钟数据恢复电路的相位插值器公开(公告)号：US20140037035A1
公开(公告)日：2014-02-06
申请号：US13564758
申请日：2012-08-02
申请人： Tao Wen CHUNG , Chan-Hong CHERN , Ming-Chieh HUANG , Chih-Chang LIN , Yuwen SWEI
发明人： Tao Wen CHUNG , Chan-Hong CHERN , Ming-Chieh HUANG , Chih-Chang LIN , Yuwen SWEI
IPC分类号： H03D3/24
CPC分类号： H03K5/135 , H03H11/20 , H03K2005/00052 , H04L7/0029
摘要： A phase interpolator for a CDR circuit produces an output clock having level transitions between the level transitions on two input clocks. The input clocks drive cross-coupled differential amplifiers with an output that can be varied in phase by variable current throttling or steering, according to an input control value. The differential amplifiers produce an output signal with a transition spanning a time between the start of a transition on the leading input clock up to the end of the transition on the lagging input clock. The output clock is linear so long as the transitions on the two input clocks overlap. Active integrators each having an amplifier with a series resistance and capacitive feedback path are coupled to each input to the cross-coupled differential amplifiers, which enhances overlap of the input clock rise times and improves the linearity of the interpolated output signal.
摘要翻译： 用于CDR电路的相位插值器产生具有在两个输入时钟上的电平转换之间的电平转换的输出时钟。 输入时钟驱动交叉耦合差分放大器，输出可根据输入控制值通过可变电流节流或转向相位变化。 差分放大器产生一个输出信号，该输出信号跨越在引导输入时钟之间的转换开始到延迟输入时钟转换结束之间的时间。 输出时钟是线性的，只要两个输入时钟的转换重叠即可。 每个具有串联电阻和电容反馈路径的放大器的积分器耦合到交叉耦合差分放大器的每个输入，这增强了输入时钟上升时间的重叠，并提高了内插输出信号的线性度。
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公开(公告)号：US20120032731A1
公开(公告)日：2012-02-09
申请号：US12849503
申请日：2010-08-03
CPC分类号： H02M3/07
摘要： An integrated circuit includes a first PMOS transistor, where its drain is arranged to be coupled to a voltage output, and its source is coupled to the drain of a second PMOS transistor. The source of the second PMOS transistor is arranged to be coupled to a high power supply voltage. The source and drain of a MOS capacitor are coupled to the source of the first PMOS transistor. The drain of an NMOS transistor is coupled to the drain of the first PMOS transistor. The integrated circuit is configured to receive a voltage input to generate the voltage output having a maximum voltage higher than the voltage input. The gate oxide layer thickness of the MOS capacitor is less than that of the first PMOS transistor.
摘要翻译： 集成电路包括第一PMOS晶体管，其中其漏极被布置成耦合到电压输出，并且其源极耦合到第二PMOS晶体管的漏极。 第二PMOS晶体管的源极被布置成耦合到高电源电压。 MOS电容器的源极和漏极耦合到第一PMOS晶体管的源极。 NMOS晶体管的漏极耦合到第一PMOS晶体管的漏极。 集成电路被配置为接收电压输入以产生具有高于电压输入的最大电压的电压输出。 MOS电容器的栅氧化层厚度小于第一PMOS晶体管的栅极氧化层厚度。
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公开(公告)号：US20120013374A1
公开(公告)日：2012-01-19
申请号：US12835130
申请日：2010-07-13
IPC分类号： H03L7/06
摘要： Some embodiments regard a circuit comprising: a first circuit configured to lock a frequency of an output clock to a frequency of a reference clock; a second circuit configured to align an input signal to a phase clock of the output clock; a third circuit configured to use a first set of phase clocks of the output clock and a second set of phase clocks of the output clock to improve alignment of the input signal to the phase clock of the output clock; and a lock detection circuit configured to turn on the first circuit when the frequency of the output clock is not locked to the frequency of the reference clock; and to turn off the first circuit and to turn on the second circuit and the third circuit when the frequency of the output clock is locked to the frequency of the reference clock.
摘要翻译： 一些实施例涉及一种电路，包括：第一电路，其被配置为将输出时钟的频率锁定到参考时钟的频率; 第二电路，被配置为将输入信号与所述输出时钟的相位时钟对准; 第三电路，被配置为使用所述输出时钟的第一组相位时钟和所述输出时钟的第二组相位时钟，以改善所述输入信号与所述输出时钟的相位时钟的对准; 以及锁定检测电路，被配置为当所述输出时钟的频率未被锁定到所述参考时钟的频率时接通所述第一电路; 并且当输出时钟的频率被锁定到参考时钟的频率时，关闭第一电路并接通第二电路和第三电路。
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