公开(公告)号：US20130024745A1

公开(公告)日：2013-01-24

申请号：US13609984

申请日：2012-09-11

申请人： Eran Sharon ,  Simon Litsyn ,  Idan Alrod

发明人： Eran Sharon ,  Simon Litsyn ,  Idan Alrod

IPC分类号： H03M13/05

CPC分类号： H03M13/114 ,  H03M13/6505

摘要： To decode a representation of a codeword that encodes K information bits as N>K codeword bits, messages are exchanged between N bit nodes and N−K check nodes of a graph in which E edges connect the bit nodes and the check nodes. While messages are exchanged, fewer than E of the messages are stored, and/or fewer than N soft estimates of the codeword bits are stored. In some embodiments, the messages are exchanged only within sub-graphs and between the sub-graphs and one or more external check nodes. While messages are exchanged, the largest number of stored messages is the number of edges in the sub-graph with the most edges plus the number of edges that connect the sub-graphs to the external check node(s), and/or the largest number of stored soft estimates is the number of bit nodes in the sub-graph with the most bit nodes.

摘要翻译： 为了将编码K个信息比特的码字的表示解码为N个K个码字比特，消息在其中E个边缘连接比特节点和校验节点的图的N个比特节点和N-K个校验节点之间进行交换。 当消息被交换时，存储少于E个消息，和/或存储少于N个码字比特的软估计。 在一些实施例中，消息仅在子图中以及子图和一个或多个外部校验节点之间交换。 当消息被交换时，最大数量的存储消息是具有最多边缘的子图中的边数加上将子图连接到外部校验节点的边数，和/或最大 存储的软估计数是具有最多位节点的子图中的比特节点的数量。

公开(公告)号：US08315091B2

公开(公告)日：2012-11-20

申请号：US13152001

申请日：2011-06-02

申请人： Eran Sharon ,  Idan Alrod

发明人： Eran Sharon ,  Idan Alrod

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C16/06

CPC分类号： G11C29/16 ,  G11C16/04 ,  G11C29/50

摘要： A storage device includes a plurality of memory elements and a controller. The controller is configured to receive measured characteristics of the memory elements. The measured characteristics correspond to a plurality of values including a first value stored at a first memory element of the plurality of memory elements and a second value stored at a second memory element of the plurality of memory elements. The controller is configured to test whether at least some of the plurality of values match a particular pattern correlated to a disturb condition at the first memory element. The controller is configured to provide a data value corresponding to the first memory element, where the data value is determined at least in part based on a result of the test.

摘要翻译： 存储装置包括多个存储元件和控制器。 控制器被配置为接收存储元件的测量特性。 所测量的特性对应于多个值，包括存储在多个存储元件中的第一存储元件上的第一值和存储在多个存储元件中的第二存储元件上的第二值。 控制器被配置为测试多个值中的至少一些值是否匹配与第一存储器元件处的干扰条件相关的特定模式。 控制器被配置为提供对应于第一存储器元件的数据值，其中基于测试的结果至少部分地确定数据值。

公开(公告)号：US08085590B2

公开(公告)日：2011-12-27

申请号：US12906095

申请日：2010-10-17

申请人： Simon Litsyn ,  Eran Sharon ,  Idan Alrod

发明人： Simon Litsyn ,  Eran Sharon ,  Idan Alrod

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C16/06

CPC分类号： G11C16/10 ,  G06F11/1072 ,  G11C7/1006 ,  G11C11/56 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/34 ,  G11C29/42 ,  G11C2211/5641

摘要： To store a plurality of input bits, the bits are mapped to a corresponding programmed state of one or more memory cells and the cell(s) is/are programmed to that corresponding programmed state. The mapping may be many-to-one or may be an “into” generalized Gray mapping. The cell(s) is/are read to provide a read state value that is transformed into a plurality of output bits, for example by maximum likelihood decoding or by mapping the read state value into a plurality of soft bits and then decoding the soft bits.

摘要翻译： 为了存储多个输入位，这些位被映射到一个或多个存储器单元的相应的编程状态，并且单元被编程为相应的编程状态。 映射可以是多对一的或者可以是“到”广义灰色映射。 读取单元以提供被转换成多个输出位的读取状态值，例如通过最大似然解码或通过将读取状态值映射到多个软比特中，然后解码软比特 。

公开(公告)号：US20110276856A1

公开(公告)日：2011-11-10

申请号：US13170193

申请日：2011-06-28

申请人： Simon LITSYN ,  Eran SHARON ,  Idan ALROD ,  Menahem LASSER

发明人： Simon LITSYN ,  Eran SHARON ,  Idan ALROD ,  Menahem LASSER

IPC分类号： H03M13/05 ,  G06F11/10

CPC分类号： H03M13/2927 ,  G06F11/1068 ,  H03M13/1111 ,  H03M13/152 ,  H03M13/1545 ,  H03M13/2903 ,  H03M13/2906 ,  H03M13/3715 ,  H03M13/6362

摘要： Data bits to be encoded are split into a plurality of subgroups. Each subgroup is encoded separately to generate a corresponding codeword. Selected subsets are removed from the corresponding codewords, leaving behind shortened codewords, and are many-to-one transformed to condensed bits. The final codeword is a combination of the shortened codewords and the condensed bits. A representation of the final codeword is decoded by being partitioned to a selected subset and a plurality of remaining subsets. Each remaining subset is decoded separately. If one of the decodings fails, the remaining subset whose decoding failed is decoded at least in part according to the selected subset. If the encoding and decoding are systematic then the selected subsets are of parity bits.

摘要翻译： 要编码的数据位被分割成多个子组。 每个子组被分别编码以产生相应的码字。 所选择的子集从相应的码字中移除，留下缩短的码字，并且被多对一地转换成浓缩比特。 最终码字是缩短的码字和浓缩比特的组合。 最终码字的表示被分割成选定的子集和多个剩余子集。 每个剩余子集被单独解码。 如果解码失败之一，则解码失败的剩余子集至少部分地根据所选子集进行解码。 如果编码和解码是系统的，则所选择的子集是奇偶校验位。

公开(公告)号：US20110276749A1

公开(公告)日：2011-11-10

申请号：US13175859

申请日：2011-07-03

申请人： Simon LITSYN ,  Eran SHARON ,  Idan ALROD

发明人： Simon LITSYN ,  Eran SHARON ,  Idan ALROD

IPC分类号： G06F12/02

CPC分类号： G11C16/10 ,  G06F11/1072 ,  G11C7/1006 ,  G11C11/56 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/34 ,  G11C29/42 ,  G11C2211/5641

摘要： To store a plurality of input bits, the bits are mapped to a corresponding programmed state of one or more memory cells and the cell(s) is/are programmed to that corresponding programmed state. The mapping may be many-to-one or may be an “into” generalized Gray mapping. The cell(s) is/are read to provide a read state value that is transformed into a plurality of output bits, for example by maximum likelihood decoding or by mapping the read state value into a plurality of soft bits and then decoding the soft bits.

公开(公告)号：US20110182118A1

公开(公告)日：2011-07-28

申请号：US13031221

申请日：2011-02-20

申请人： Simon Litsyn ,  Idan Alrod ,  Eran Sharon

发明人： Simon Litsyn ,  Idan Alrod ,  Eran Sharon

IPC分类号： G11C16/06

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/28 ,  G11C2211/5634

摘要： Each of a plurality of flash memory cells is programmed to a respective one of L≧2 threshold voltage states within a threshold voltage window. Values of parameters of threshold voltage functions are adjusted in accordance with comparisons of the threshold voltages of some or all of the cells to two or more of m≧2 threshold voltage intervals within the threshold voltage window. Reference voltages for reading the cells are selected based on the values. Alternatively, the m threshold voltage intervals span the threshold voltage window, and respective threshold voltage states are assigned to the cells based on numbers of cells whose threshold voltages are in the intervals, without re-reading the cells.

摘要翻译： 多个闪存单元中的每一个被编程为阈值电压窗口内的L≥2个阈值电压状态中的相应一个。 根据阈值电压窗口内的一些或所有单元的阈值电压与两个或多个m≥2个阈值电压间隔的比较，来调整阈值电压函数的参数值。 基于这些值来选择用于读取单元的参考电压。 或者，m阈值电压间隔跨越阈值电压窗口，并且基于阈值电压处于间隔中的单元的数量而将各个阈值电压状态分配给单元，而不重新读取单元。

公开(公告)号：US07984360B2

公开(公告)日：2011-07-19

申请号：US11876789

申请日：2007-10-23

申请人： Eran Sharon ,  Simon Litsyn ,  Idan Alrod

发明人： Eran Sharon ,  Simon Litsyn ,  Idan Alrod

IPC分类号： G11C29/00

CPC分类号： G11C11/5628 ,  G06F11/1072 ,  G11C7/1006 ,  G11C29/00

摘要： To store an input string of M N-tuples of bits, a substitution transformation is selected in accordance with the input string and is applied to the input string to provide a transformed string of M N-tuples of bits. M or more memory cells are programmed to represent the transformed string and preferably also to represent a key of the transformation. Alternatively, the memory selectively programs each of M or more cells to a respective one of 2N states. A mapping that maps the binary numbers in [0,2N−1] into respective states is selected in accordance with the input string and is used to program M cells to represent the input string. Preferably, a key of the mapping is stored in the memory in association with the M cells.

摘要翻译： 为了存储M个N元组的输入串，根据输入字符串选择替换变换，并将其应用于输入字符串，以提供M个N元组的变换字符串。 M个或更多个存储器单元被编程以表示变换的字符串，并且优选地也表示转换的关键字。 或者，存储器选择性地将M个或更多个单元中的每一个编程为2N个状态中的相应一个。 根据输入字符串选择将[0,2N-1]中的二进制数映射到各自状态的映射，并用于对M个单元进行编程以表示输入字符串。 优选地，映射的密钥与M个单元相关联地存储在存储器中。

公开(公告)号：US20110022927A1

公开(公告)日：2011-01-27

申请号：US12553117

申请日：2009-09-03

申请人： Eran Sharon ,  Idan Alrod ,  Simon Litsyn

发明人： Eran Sharon ,  Idan Alrod ,  Simon Litsyn

IPC分类号： H03M13/05 ,  G06F11/10

CPC分类号： H03M13/1174 ,  G06F11/1068 ,  H03M13/1105 ,  H03M13/1157 ,  H03M13/3707 ,  H03M13/6306 ,  H03M13/6362 ,  H03M13/6502

摘要： k information bits are encoded according to a code with which is associated a parity check matrix H that has n columns. The entire resulting codeword is stored in a storage medium. At least n′

摘要翻译： k个信息比特，根据与相关联的是具有n列的奇偶校验矩阵H的代码来编码。 整个结果码字被存储在存储介质中。 至少n'<所述码字的表示的n位被从存储介质读出并试图仅在n解码'使用矩阵H'具有比H.更少的列通常，H具有m个位=正 -k行和H'具有m-（n-n'）行和n'列。 如果尝试失败，一个或多个额外的比特被从存储介质读出，必要时，和与n合并'比特，并且使用矩阵H被重复解码尝试'“，其具有比H'更多的列。

公开(公告)号：US20100332956A1

公开(公告)日：2010-12-30

申请号：US12495654

申请日：2009-06-30

申请人： IDAN ALROD ,  ERAN SHARON

发明人： IDAN ALROD ,  ERAN SHARON

IPC分类号： H03M13/07 ,  G06F11/10

CPC分类号： H03M13/1555 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/158 ,  H03M13/159 ,  H03M13/6561

摘要： Systems and methods to perform polynomial division are disclosed. In a particular embodiment, the method includes receiving a codeword and storing a portion of the received codeword at a register. The portion of the received codeword has a first number of terms. A divisor having a second number of terms is also received. During at least one stage of a multi-stage polynomial division operation using the portion of the codeword and the divisor, the portion of the received codeword to be divided by the divisor is adjusted based on a result of a comparison of the first number to the second number.

摘要翻译： 公开了执行多项式除法的系统和方法。 在特定实施例中，该方法包括接收码字并将接收的码字的一部分存储在寄存器中。 所接收的码字的部分具有第一数目的项。 还收到了具有第二数目条款的除数。 在使用码字和除数的部分的多阶段多项式除法运算的至少一个阶段期间，基于第一个数字与第二个数字的比较的结果来调整要除以除数的接收码字的部分 第二个数字。

公开(公告)号：US20100192042A1

公开(公告)日：2010-07-29

申请号：US12645499

申请日：2009-12-23

申请人： Eran SHARON ,  Idan ALROD ,  Simon LITSYN

发明人： Eran SHARON ,  Idan ALROD ,  Simon LITSYN

IPC分类号： H03M13/05 ,  G06F11/10

CPC分类号： G11C16/26 ,  G06F11/1068 ,  G11C11/5642 ,  G11C29/00

摘要： To read memory cells that have been programmed to store an ECC codeword, with each cell storing a respective plurality of bits of the codeword, a respective value of an operational parameter such as a threshold voltage of each cell is measured. Each bit is assigned a respective metric, such as a LLR estimate of the bit, based at least in part on the respective value of the operational parameter of the bit's cell. The metrics are decoded with reference both to the ECC and to mutual constraints of the metrics within each cell that are independent of the ECC.

摘要翻译： 为了读取已编程为存储ECC码字的存储器单元，其中每个单元存储码字的相应多个位，测量诸如每个单元的阈值电压的操作参数的相应值。 至少部分地基于比特的小区的操作参数的相应值，为比特分配各个度量，例如比特的LLR估计。 参考ECC和与独立于ECC的每个单元内的度量的相互约束来对度量进行解码。