公开(公告)号：US20090122621A1

公开(公告)日：2009-05-14

申请号：US12170206

申请日：2008-07-09

Applicant: Kwang-Myoung Rho ,  Jae-Jin Lee

Inventor： Kwang-Myoung Rho ,  Jae-Jin Lee

IPC: G11C7/10 ,  H03K19/0175

CPC classification number: G11C7/1078 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1084 ,  H03K19/018521

Abstract: A circuit for controlling a signal line transmitting data. The circuit includes a data level controller that, when the level of the data transmitted through the signal line is changed, controls the level of the data to be lower than an external power supply voltage level and higher than a ground voltage level after a predetermined time.

Abstract translation: 用于控制发送数据的信号线的电路。 该电路包括数据电平控制器，当通过信号线传输的数据的电平改变时，数据电平低于外部电源电压并且在预定时间之后高于接地电压电平 。

公开(公告)号：US07526637B2

公开(公告)日：2009-04-28

申请号：US11453288

申请日：2006-06-15

Applicant: Chang Hee Jung ,  Dae Seob Lim ,  Jae Jin Lee ,  Sang Yong Han

Inventor： Chang Hee Jung ,  Dae Seob Lim ,  Jae Jin Lee ,  Sang Yong Han

IPC: G06F9/00

CPC classification number: G06F8/456 ,  G06F9/5066 ,  G06F11/3404 ,  G06F2201/88

Abstract: Provided is a parallel program execution method in which in order to reflect structural characteristics of a multithreaded processor-based parallel system, performance of the parallel loop is predicted while compiling or executing using a performance prediction model and then the parallel program is executed using an adaptive execution method.The method includes the steps of: generating as many threads as the number of physical processors of the parallel system in order to execute at least one parallel loop contained in the parallel program; by the generated threads, executing at least one single loop of each parallel loop; measuring an execution time, the number of executed instructions, and the number of cache misses for each parallel loop; determining an execution mode of each parallel loop by determining the number of threads used to execute each parallel loop based on the measured values; and allocating the threads to each physical processor according to the result of the determination to execute each parallel loop.The method significantly improves the performance of the parallel program driven in the multithreaded processor-based parallel system.

Abstract translation: 提供了一种并行程序执行方法，其中为了反映基于多线程处理器的并行系统的结构特征，在使用性能预测模型编译或执行时预测并行循环的性能，然后使用自适应 执行方式。 该方法包括以下步骤：生成与并行系统的物理处理器的数量一样多的线程，以便执行并行程序中包含的至少一个并行循环; 通过生成的线程执行每个并行循环的至少一个单个循环; 测量执行时间，执行指令的数量以及每个并行循环的高速缓存未命中数; 通过基于测量值确定用于执行每个并行循环的线程数，确定每个并行循环的执行模式; 以及根据确定的结果将线程分配给每个物理处理器以执行每个并行循环。 该方法显着提高了在基于多线程处理器的并行系统中驱动的并行程序的性能。

公开(公告)号：US07305516B2

公开(公告)日：2007-12-04

申请号：US10877887

申请日：2004-06-25

Applicant: Ihl-Ho Lee ,  Kyung-Whan Kim ,  Jae-Jin Lee

Inventor： Ihl-Ho Lee ,  Kyung-Whan Kim ,  Jae-Jin Lee

IPC: G06F12/00

CPC classification number: G11C7/1048 ,  G11C7/1075 ,  G11C7/20 ,  G11C11/4072 ,  G11C11/4096

Abstract: There is provided a multi-port memory device, which is capable of preventing a first high data fail phenomenon at an initial operation in a current sensing type global data bus transmission/reception structure without causing a problem in a low data transmission. In the multi-port memory device having a data transmission/reception block (bank, port, global data bus connection block, etc.) which exchanges data with the global data bus in a current sensing type data transmission/reception structure, an initialization switch is used to discharge each global data bus line and an initialization signal generator controls the initialization switch. A first high data fail at the initial operation is caused by a high precharge level of the global data bus. According to the present invention, it is possible to lower a high precharge level without causing a problem in data transmission.

Abstract translation: 提供了一种多端口存储器件，其能够在电流感测型全局数据总线发送/接收结构中的初始操作时防止第一高数据故障现象，而不会导致低数据传输中的问题。 在具有在当前感测型数据发送/接收结构中与全局数据总线交换数据的数据发送/接收块（存储体，端口，全局数据总线连接块等）的多端口存储器件中，初始化开关 用于放电每个全局数据总线，初始化信号发生器控制初始化开关。 初始操作时的第一个高数据故障是由全局数据总线的高预充电电平引起的。 根据本发明，可以在不引起数据传输的问题的情况下降低高预充电水平。

公开(公告)号：US20070211833A1

公开(公告)日：2007-09-13

申请号：US11683635

申请日：2007-03-08

Applicant: Joo-hyun LEE ,  Jae-jin LEE ,  Jong-yun YUN

Inventor： Joo-hyun LEE ,  Jae-jin LEE ,  Jong-yun YUN

IPC: H03D1/00

CPC classification number: G11B20/10009 ,  G11B20/10046 ,  G11B20/10287 ,  G11B20/10296 ,  G11B20/10481 ,  G11B2220/2516 ,  G11B2220/2537

Abstract: A method and an apparatus to detect data in a data storage device, and a method and an apparatus to effectively detect data in channels having characteristics in which bands of data to be reproduced are limited. The method includes partially selecting partial paths from paths of a Viterbi trellis having a number corresponding to an order of a polynomial used in equalization, in an order where path metric values increase from a path having a minimum path metric value, deciding a best path having a minimum path metric value among the partial paths, and detecting data based on the best path.

Abstract translation: 一种检测数据存储装置中的数据的方法和装置，以及有效地检测具有特征的数据的方法和装置，其中要再现的数据频带受到限制。 该方法包括从路径度量值从具有最小路径度量值的路径增加的顺序，部分地从具有对应于均衡中使用的多项式的阶数的维度比特网格的路径中选择部分路径，从而确定具有 部分路径中的最小路径度量值，以及基于最佳路径检测数据。

公开(公告)号：US07269041B2

公开(公告)日：2007-09-11

申请号：US11322508

申请日：2005-12-30

Applicant: Kyung-Whan Kim ,  Jae-Jin Lee

Inventor： Kyung-Whan Kim ,  Jae-Jin Lee

IPC: G11C5/02

CPC classification number: G11C8/16 ,  G11C7/1048 ,  G11C7/1075

Abstract: A multi-port memory device that prevents degradation of efficiency of a global data drive by turning off the switches, which do not discharge a global data bus. The multi-port memory device includes a global data bus, a banks, each bank including a transmitter and a receiver; ports, each port including a transmitter and a receiver; switches that operate to selectively connect the receivers of the banks and ports to the global data bus; and a switch signal generator for generating a switch signal in response to data drive pulses inputted to the transmitters of the banks and the ports.

Abstract translation: 一种多端口存储器件，通过关闭不释放全局数据总线的开关来防止全局数据驱动器的效率降低。 多端口存储器件包括全局数据总线，存储体，每个存储体包括发射器和接收器; 端口，每个端口包括发射机和接收机; 用于选择性地将存储体和端口的接收器连接到全局数据总线的开关; 以及开关信号发生器，用于响应于输入到所述存储体和所述端口的发射器的数据驱动脉冲而产生开关信号。

公开(公告)号：US07254087B2

公开(公告)日：2007-08-07

申请号：US11322789

申请日：2005-12-29

Applicant: Kyung-Whan Kim ,  Jae-Jin Lee

Inventor： Kyung-Whan Kim ,  Jae-Jin Lee

IPC: G11C8/00

CPC classification number: G11C7/1075

Abstract: A multi-port memory device improves efficiency of a global data drive by controlling the global data bus to transmit data in a predetermined range. The multi-port memory device includes a global data bus; transmitters and receivers; a termination unit for controlling the global data bus to transmit the data in a range between a first voltage and a second voltage in response to an active mode signal; and a voltage generator for generating the first and the second voltages. The first voltage is higher than a ground voltage and the second voltage is lower than a power supply voltage.

Abstract translation: 多端口存储器件通过控制全局数据总线在预定范围内传输数据来提高全局数据驱动的效率。 多端口存储器件包括全局数据总线; 发射机和接收机; 终端单元，用于响应于活动模式信号，控制全局数据总线在第一电压和第二电压之间的范围内传输数据; 以及用于产生第一和第二电压的电压发生器。 第一电压高于接地电压，第二电压低于电源电压。

公开(公告)号：US20070041258A1

公开(公告)日：2007-02-22

申请号：US11589038

申请日：2006-10-30

Applicant: Dong-Keun Kim ,  Jae-Jin Lee

Inventor： Dong-Keun Kim ,  Jae-Jin Lee

IPC: G11C7/02

CPC classification number: G11C7/1069 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/1096 ,  G11C7/18 ,  G11C2207/105

Abstract: A semiconductor memory device with a reduced cell area and a high-speed data transfer by modifying a circuit layout. The semiconductor memory device includes: a cell area with a first and a second cell areas; a plurality of Y decoders of which one Y decoder selects bit line sense amplifiers in the first and the second cell areas; IO sense amplifiers provided with a first IO sense amplifier and a second IO sense amplifier; a plurality of first data lines for transferring a data sensed and amplified at the bit line sense amplifier of the first cell area; and a plurality of second data lines for transferring a data sensed and amplified at the bit line sense amplifier of the second cell area.

Abstract translation: 一种通过修改电路布局具有减小的单元面积和高速数据传输的半导体存储器件。 半导体存储器件包括：具有第一和第二单元区域的单元区域; 多个Y解码器，其中一个Y解码器在第一和第二单元区域中选择位线读出放大器; 具有第一IO读出放大器和第二IO读出放大器的IO读出放大器; 多个第一数据线，用于传送在第一单元区域的位线读出放大器处感测和放大的数据; 以及多个第二数据线，用于传送在第二单元区域的位线读出放大器处感测和放大的数据。

公开(公告)号：US07126185B2

公开(公告)日：2006-10-24

申请号：US11115135

申请日：2005-04-27

Applicant: Hee Bok Kang ,  Jin Hong Ahn ,  Jae Jin Lee

Inventor： Hee Bok Kang ,  Jin Hong Ahn ,  Jae Jin Lee

IPC: H01L29/788

CPC classification number: G11C16/0483 ,  G11C16/0466 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/7881 ,  H01L29/792 ,  H01L29/8616

Abstract: A charge trap insulator memory device comprises a plurality of memory cells connected serially, a first switching device, and a second switching device. In the plurality of memory cells, data applied through a bit line depending on potentials applied to a top word line and a bottom word line are stored in a charge trap insulator or the data stored in the charge trap insulator are outputted to the bit line. The first switching element selectively connects the plurality of memory cells to the bit line in response to a first selecting signal. The second switching element selectively connects the plurality of memory cells to a sensing line in response to a second selecting signal.

公开(公告)号：US07091769B2

公开(公告)日：2006-08-15

申请号：US10626766

申请日：2003-07-25

Applicant: Myeong Ju Kwon ,  Jae Jin Lee

Inventor： Myeong Ju Kwon ,  Jae Jin Lee

IPC: G05F1/10

CPC classification number: H02M3/073 ,  H02M2003/077

Abstract: A voltage generator with reduced noise features a detector, a controller, a sub-booster, a main booster and a voltage adder. The detector receives an output voltage, a first reference voltage and a second reference voltage lower than the first reference voltage, and then outputs a first sensing signal and a second sensing signal. The controller receives the first sensing signal and the second sensing signal and an action signal to output a first control signal and a second control signal. The sub-booster boosts a voltage in response of the first control signal. The main booster boosts a voltage in response to the second control signal. The voltage adder adds output signals from the sub-booster and main booster, to provide the output voltage.

Abstract translation: 具有降低噪声的电压发生器具有检测器，控制器，副升压器，主升压器和电压加法器。 检测器接收输出电压，第一参考电压和低于第一参考电压的第二参考电压，然后输出第一感测信号和第二感测信号。 控制器接收第一感测信号和第二感测信号以及动作信号，以输出第一控制信号和第二控制信号。 副升压器响应于第一控制信号而升高电压。 主增压器响应于第二控制信号而升高电压。 电压加法器将来自副升压器和主升压器的输出信号相加，以提供输出电压。

公开(公告)号：US07031202B2

公开(公告)日：2006-04-18

申请号：US10744257

申请日：2003-12-22

Applicant: Seok-Cheol Yoon ,  Jae-Jin Lee

Inventor： Seok-Cheol Yoon ,  Jae-Jin Lee

IPC: G11C11/34

CPC classification number: G11C11/4085 ,  G11C8/08 ,  G11C11/406 ,  G11C2211/4068

Abstract: The present relates to a memory device; and, more particularly, to an apparatus and a method for preventing a loss of reliability of data, which are stored in memory cell, at the time of restoring and writing the data. The semiconductor memory device according to the present invention comprises: a high voltage generator for boosting an external voltage level and then for producing a first high voltage level; a pumping control signal generator for issuing a pumping control signal, which is activated in a restore section and a write section, in response to a command signal; a pumping unit for outputting the first high voltage level from the high voltage generator or for boosting the high voltage level in order to generate a second high voltage plus level in response to the pumping control signal from the pumping control signal generator, wherein the second high voltage plus level is higher than the first high voltage level; and a word line driver for driving the word line WL using the first high voltage level and for driving the word line WL using the second high voltage plus level from the pumping unit in the restore and write sections.

Abstract translation: 本发明涉及一种存储装置; 更具体地，涉及在恢复和写入数据时防止存储在存储单元中的数据的可靠性损失的装置和方法。 根据本发明的半导体存储器件包括：高压发生器，用于升高外部电压电平，然后产生第一高电压电平; 泵送控制信号发生器，用于响应于命令信号发出在恢复部分和写入部分中激活的泵送控制信号; 泵送单元，用于从高压发生器输出第一高电压电平或用于升高高电压电平，以便响应于来自泵送控制信号发生器的泵送控制信号产生第二高电压加电平，其中第二高电平 电压加电平高于第一高电压电平; 以及字线驱动器，用于使用第一高电压电平驱动字线WL，并且使用来自恢复和写入部分中的泵送单元的第二高电压加电平来驱动字线WL。