公开(公告)号：US20060040485A1

公开(公告)日：2006-02-23

申请号：US11201421

申请日：2005-08-11

Applicant: Jang-Eun Lee ,  Sung-Lae Cho ,  Jeong-Hee Park

Inventor： Jang-Eun Lee ,  Sung-Lae Cho ,  Jeong-Hee Park

IPC: H01L21/44

CPC classification number: H01L21/76877 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/143 ,  H01L45/144 ,  H01L45/1683

Abstract: Provided are methods for forming conductive plug structures, such as via plugs, from a plurality of conductive layer patterns and methods of fabricating semiconductor devices, including semiconductor memory devices such as phase change semiconductor memory devices. An example method forms a small via structure by forming a conductive layer on a semiconductor substrate. A molding insulating layer is formed on the conductive layer and a via hole is formed through the insulating layer to expose a region of the conductive layer. A first via filling layer is formed and then partially removed to form a partial via plug. The formation and removal of the phase change material layer are then repeated as necessary to form a multilayer plug structure that substantially fills the via hole with the multilayer structure typically exhibiting reduced defects and damage than plug structures prepared by conventional methods.

公开(公告)号：US20060027846A1

公开(公告)日：2006-02-09

申请号：US11145478

申请日：2005-06-03

Applicant: Jang-Eun Lee ,  Se-Chung Oh ,  Jun-Soo Bae ,  Hyun-Jo Kim ,  Young-Ki Ha ,  Kyung-Tae Nam

Inventor： Jang-Eun Lee ,  Se-Chung Oh ,  Jun-Soo Bae ,  Hyun-Jo Kim ,  Young-Ki Ha ,  Kyung-Tae Nam

IPC: H01L29/94

CPC classification number: H01L27/228 ,  B82Y10/00 ,  G11C11/161

Abstract: A magnetic random access memory device may include a semiconductor substrate, a magnetic tunnel junction (MTJ) structure, a contact plug, and a digit line. More particularly, the MTJ structure may be on the semiconductor substrate, and the digit line may be adjacent the magnetic tunnel junction structure. In addition, the contact plug may provide electrical connection between the magnetic tunnel junction structure and the semiconductor substrate, and the contact plug may be between the magnetic tunnel junction structure and the semiconductor substrate. Related methods are also discussed.

Abstract translation: 磁性随机存取存储器件可以包括半导体衬底，磁性隧道结（MTJ）结构，接触插塞和数字线。 更具体地，MTJ结构可以在半导体衬底上，并且数字线可以与磁性隧道结结构相邻。 此外，接触插头可以在磁性隧道结结构和半导体衬底之间提供电连接，并且接触插塞可以在磁性隧道结结构和半导体衬底之间。 还讨论了相关方法。

公开(公告)号：US20050146967A1

公开(公告)日：2005-07-07

申请号：US10971704

申请日：2004-10-25

Applicant: Sang-jin Park ,  Tae-wan Kim ,  Wan-jun Park ,  Jang-eun Lee

Inventor： Sang-jin Park ,  Tae-wan Kim ,  Wan-jun Park ,  Jang-eun Lee

IPC: H01L27/105 ,  G11C11/15 ,  H01L21/8246 ,  H01L27/115 ,  H01L43/08

CPC classification number: H01L43/08 ,  G11C11/15 ,  H01L43/12

Abstract: A magnetic random access memory (MRAM), and a method of manufacturing the same, includes a switching device and a magnetic tunneling junction (MTJ) cell connected to the switching device, wherein the MTJ cell includes a pinned film having a metal film and a magnetic film, the magnetic film enclosing the metal film.

Abstract translation: 磁性随机存取存储器（MRAM）及其制造方法包括连接到开关器件的开关器件和磁性隧道结（MTJ）单元，其中MTJ单元包括具有金属膜和 磁膜，磁膜封闭金属膜。

公开(公告)号：US20050006682A1

公开(公告)日：2005-01-13

申请号：US10888964

申请日：2004-07-09

Applicant: Jun-Soo Bae ,  Jang-Eun Lee ,  Hyun-Jo Kim ,  In-Gyu Baek ,  Young-Ki Ha

Inventor： Jun-Soo Bae ,  Jang-Eun Lee ,  Hyun-Jo Kim ,  In-Gyu Baek ,  Young-Ki Ha

IPC: G11C11/15 ,  G11C11/16 ,  H01F10/32 ,  H01F41/30 ,  H01L43/08 ,  H01L43/12 ,  H01L29/76 ,  G11B5/127

CPC classification number: B82Y25/00 ,  B82Y10/00 ,  G11B5/3909 ,  G11C11/16 ,  H01F10/3254 ,  H01F41/302 ,  H01L43/08 ,  H01L43/12

Abstract: Magnetic Random Access Memory (MRAM) devices include a lower electrode and a magnetic tunnel junction on the lower electrode. The magnetic tunnel junction includes a seed layer and a tunneling barrier that is oriented in a same direction as the most closely packed plane direction of the seed layer. An oxide layer may be provided between the lower electrode and the magnetic tunnel junction. The lower electrode may be a titanium-rich TiN layer having more than 50 atomic percent titanium content. Analogous fabrication methods are also described.

Abstract translation: 磁性随机存取存储器（MRAM）器件包括下电极和下电极上的磁隧道结。 磁性隧道结包括种子层和隧道势垒，其定向在与种子层的最紧密堆积的平面方向相同的方向上。 可以在下电极和磁隧道结之间提供氧化物层。 下电极可以是具有超过50原子％钛含量的富钛TiN层。 还描述了类似的制造方法。

公开(公告)号：US06797109B2

公开(公告)日：2004-09-28

申请号：US10235976

申请日：2002-09-06

Applicant: Jeong-hyuck Park ,  Hee-duk Kim ,  Jung-hun Cho ,  Jong-wook Choi ,  Sung-bum Cho ,  Young-koo Lee ,  Jin-sung Kim ,  Jang-eun Lee ,  Ju-hyuck Chung ,  Sun-hoo Park ,  Jae-hyun Lee ,  Shin-woo Nam

Inventor： Jeong-hyuck Park ,  Hee-duk Kim ,  Jung-hun Cho ,  Jong-wook Choi ,  Sung-bum Cho ,  Young-koo Lee ,  Jin-sung Kim ,  Jang-eun Lee ,  Ju-hyuck Chung ,  Sun-hoo Park ,  Jae-hyun Lee ,  Shin-woo Nam

IPC: H05H100

CPC classification number: H01J37/32431 ,  C23C16/4583 ,  C23C16/4585 ,  C23C16/54 ,  H01J37/32623 ,  H01J37/32642 ,  H01L21/32136 ,  H01L21/6831 ,  H01L21/68735 ,  Y10T117/10

Abstract: A process chamber used in the manufacture of a semiconductor device for etching a material layer on a semiconductor wafer includes an electrostatic chuck for holding the semiconductor wafer, and an annular edge ring which surrounds the side of the semiconductor wafer on the electrostatic chuck to prevent the semiconductor wafer from departing from its original position. The annular edge ring has a first side which faces the side of the semiconductor wafer and contacts firmly with the side of the semiconductor wafer.

Abstract translation: 用于制造用于蚀刻半导体晶片上的材料层的半导体器件的处理室包括用于保持半导体晶片的静电卡盘和围绕静电卡盘上的半导体晶片侧的环形边缘环，以防止 半导体晶片从其原始位置脱离。 环形边缘环具有面向半导体晶片的侧面并​​与半导体晶片的侧面牢固接触的​​第一侧。

公开(公告)号：US06464794B1

公开(公告)日：2002-10-15

申请号：US09404631

申请日：1999-09-23

Applicant: Jeong-hyuck Park ,  Hee-duk Kim ,  Jung-hun Cho ,  Jong-wook Choi ,  Sung-bum Cho ,  Young-koo Lee ,  Jin-sung Kim ,  Jang-eun Lee ,  Ju-hyuck Chung ,  Sun-hoo Park ,  Jae-hyun Lee ,  Shin-woo Nam

Inventor： Jeong-hyuck Park ,  Hee-duk Kim ,  Jung-hun Cho ,  Jong-wook Choi ,  Sung-bum Cho ,  Young-koo Lee ,  Jin-sung Kim ,  Jang-eun Lee ,  Ju-hyuck Chung ,  Sun-hoo Park ,  Jae-hyun Lee ,  Shin-woo Nam

IPC: C23C1600

CPC classification number: H01J37/32431 ,  C23C16/4583 ,  C23C16/4585 ,  C23C16/54 ,  H01J37/32623 ,  H01J37/32642 ,  H01L21/32136 ,  H01L21/6831 ,  H01L21/68735 ,  Y10T117/10

Abstract: A process chamber used in the manufacture of a semiconductor device for etching a material layer on a semiconductor wafer includes an electrostatic chuck for holding the semiconductor wafer, and an annular edge ring which surrounds the side of the semiconductor wafer on the electrostatic chuck to prevent the semiconductor wafer from departing from its original position. The annular edge ring has a first side which faces the side of the semiconductor wafer and contacts firmly with the side of the semiconductor wafer.

Abstract translation: 用于制造用于蚀刻半导体晶片上的材料层的半导体器件的处理室包括用于保持半导体晶片的静电卡盘和围绕静电卡盘上的半导体晶片侧的环形边缘环，以防止 半导体晶片从其原始位置脱离。 环形边缘环具有面向半导体晶片的侧面并​​与半导体晶片的侧面牢固接触的​​第一侧。