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    Method of forming via structures and method of fabricating phase change memory devices incorporating such via structures
    2.
    发明授权
    Method of forming via structures and method of fabricating phase change memory devices incorporating such via structures 有权
    形成通孔结构的方法和制造包含这种通孔结构的相变存储器件的方法

    公开(公告)号：US07473597B2

    公开(公告)日：2009-01-06

    申请号：US11201421

    申请日：2005-08-11

    申请人： Jang-Eun Lee ,  Sung-Lae Cho ,  Jeong-Hee Park

    发明人： Jang-Eun Lee ,  Sung-Lae Cho ,  Jeong-Hee Park

    IPC分类号： H01L21/44

    CPC分类号： H01L21/76877 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/143 ,  H01L45/144 ,  H01L45/1683

    摘要： Provided are methods for forming conductive plug structures, such as via plugs, from a plurality of conductive layer patterns and methods of fabricating semiconductor devices, including semiconductor memory devices such as phase change semiconductor memory devices. An example method forms a small via structure by forming a conductive layer on a semiconductor substrate. A molding insulating layer is formed on the conductive layer and a via hole is formed through the insulating layer to expose a region of the conductive layer. A first via filling layer is formed and then partially removed to form a partial via plug. The formation and removal of the phase change material layer are then repeated as necessary to form a multilayer plug structure that substantially fills the via hole with the multilayer structure typically exhibiting reduced defects and damage than plug structures prepared by conventional methods.

    摘要翻译： 提供了用于从多个导电层图案形成诸如通孔插头的导电插塞结构的方法以及制造半导体器件的方法，包括诸如相变半导体存储器件的半导体存储器件。 示例性方法通过在半导体衬底上形成导电层来形成小通孔结构。 在导电层上形成模制绝缘层，并且通过绝缘层形成通孔以暴露导电层的区域。 形成第一通孔填充层，然后部分地移除以形成部分通孔塞。 然后根据需要重复形成和除去相变材料层以形成多层插塞结构，该多层插塞结构基本上填充通孔，其中多层结构通常表现出比通过常规方法制备的插塞结构减少的缺陷和损伤。

    Method of forming resistance variable memory device
    4.
    发明授权
    Method of forming resistance variable memory device 有权
    形成电阻变量存储器件的方法

    公开(公告)号：US08580606B2

    公开(公告)日：2013-11-12

    申请号：US13241315

    申请日：2011-09-23

    申请人： Jeong-Hee Park ,  Jung-Hwan Park ,  Hideki Horii ,  Sung-Lae Cho

    发明人： Jeong-Hee Park ,  Jung-Hwan Park ,  Hideki Horii ,  Sung-Lae Cho

    IPC分类号： H01L21/06

    CPC分类号： H01L45/1625 ,  H01L27/2409 ,  H01L27/2472 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/143 ,  H01L45/144 ,  H01L45/1683

    摘要： A method of forming a resistance variable memory device, the method including forming a diode on a semiconductor substrate; forming a lower electrode on the diode; forming a first insulating film on the lower electrode, the first insulating film having an opening; forming a resistance variable film filling the opening such that the resistance variable film includes an amorphous region adjacent to a sidewall of the opening and a crystalline region adjacent to the lower electrode; and forming an upper electrode on the resistance variable film.

    摘要翻译： 一种形成电阻可变存储器件的方法，所述方法包括在半导体衬底上形成二极管; 在二极管上形成下电极; 在所述下电极上形成第一绝缘膜，所述第一绝缘膜具有开口; 形成填充所述开口的电阻变化膜，使得所述电阻变化膜包括与所述开口的侧壁相邻的非晶区域和与所述下部电极相邻的结晶区域; 并在电阻变化膜上形成上电极。

    MULTI-LAYER PHASE-CHANGEABLE MEMORY DEVICES
    6.
    发明申请
    MULTI-LAYER PHASE-CHANGEABLE MEMORY DEVICES 有权
    多层相变存储器件

    公开(公告)号：US20100019216A1

    公开(公告)日：2010-01-28

    申请号：US12568402

    申请日：2009-09-28

    申请人： Jeong-Hee Park ,  Ju-Chul Park ,  Jun-Soo Bae ,  Bong-Jin Kuh ,  Yong-Ho Ha

    发明人： Jeong-Hee Park ,  Ju-Chul Park ,  Jun-Soo Bae ,  Bong-Jin Kuh ,  Yong-Ho Ha

    IPC分类号： H01L47/00

    CPC分类号： H01L45/06 ,  G11C13/0004 ,  G11C2213/79 ,  H01L45/1233 ,  H01L45/143 ,  H01L45/144 ,  H01L45/1625 ,  H01L45/1675

    摘要： A phase-changeable memory device includes a phase-changeable material pattern and first and second electrodes electrically connected to the phase-changeable material pattern. The first and second electrodes are configured to provide an electrical signal to the phase-changeable material pattern. The phase-changeable material pattern includes a first phase-changeable material layer and a second phase-changeable material layer. The first and second phase-changeable material patterns have different chemical, physical, and/or electrical characteristics. For example, the second phase-changeable material layer may have a greater resistivity than the first phase-changeable material layer. For instance, the first phase-changeable material layer may include nitrogen at a first concentration, and the second phase-changeable material layer may include nitrogen at a second concentration that is greater than the first concentration. Related devices and fabrication methods are also discussed.

    摘要翻译： 可变相存储器件包括相变材料图案，以及电连接到相变材料图案的第一和第二电极。 第一和第二电极被配置为向相变材料图案提供电信号。 相变材料图案包括第一相变材料层和第二相变材料层。 第一和第二可相变材料图案具有不同的化学，物理和/或电特性。 例如，第二相变材料层可以具有比第一相变材料层更大的电阻率。 例如，第一相变材料层可以包括第一浓度的氮，第二相变材料层可以包括大于第一浓度的第二浓度的氮。 还讨论了相关设备和制造方法。

    Phase Change Memory Cell Employing a GeBiTe Layer as a Phase Change Material Layer, Phase Change Memory Device Including the Same, Electronic System Including the Same and Method of Fabricating the Same
    7.
    发明申请
    Phase Change Memory Cell Employing a GeBiTe Layer as a Phase Change Material Layer, Phase Change Memory Device Including the Same, Electronic System Including the Same and Method of Fabricating the Same 有权
    使用GeBiTe层作为相变材料层的相变存储单元，包括其的相变存储器件，包括其的电子系统及其制造方法

    公开(公告)号：US20070267721A1

    公开(公告)日：2007-11-22

    申请号：US11747395

    申请日：2007-05-11

    申请人： Bong-Jin Kuh ,  Yong-Ho Ha ,  Doo-Hwan Park ,  Jeong-Hee Park ,  Han-Bong Ko

    发明人： Bong-Jin Kuh ,  Yong-Ho Ha ,  Doo-Hwan Park ,  Jeong-Hee Park ,  Han-Bong Ko

    IPC分类号： H01L31/117 ,  H01L29/12

    CPC分类号： H01L45/144 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2213/72 ,  G11C2213/79 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1625

    摘要： A phase change memory cell includes an interlayer insulating layer formed on a semiconductor substrate, and a first electrode and a second electrode disposed in the interlayer insulating layer. A phase change material layer is disposed between the first and second electrodes. The phase change material layer may be an undoped GeBiTe layer, a doped GeBiTe layer containing an impurity or a doped GeTe layer containing an impurity. The undoped GeBiTe layer has a composition ratio within a range surrounded by four points (A1(Ge21.43, Bi16.67, Te61.9), A2(Ge44.51, Bi0.35, Te55.14), A3(Ge59.33, Bi0.5, Te40.17) and A4(Ge38.71, Bi16.13, Te45.16)) represented by coordinates on a triangular composition diagram having vertices of germanium (Ge), bismuth (Bi) and tellurium (Te). The doped GeBiTe layer contains an impurity and has a composition ratio within a range surrounded by four points (D1(Ge10, Bi20, Te70), D2(Ge30, Bi0, Te70), D3(Ge70, Bi0, Te30) and D4(Ge50, Bi20, Te30)) represented by coordinates on the triangular composition diagram.

    摘要翻译： 相变存储单元包括形成在半导体衬底上的层间绝缘层和设置在层间绝缘层中的第一电极和第二电极。 相变材料层设置在第一和第二电极之间。 相变材料层可以是未掺杂的GeBiTe层，包含杂质的掺杂GeBiTe层或含有杂质的掺杂GeTe层。 未掺杂的GeBiTe层的组成比在四个点（A 1（Ge 21.43，Bi 16.67，Te 61.9）， A 2（Ge 44.51，Bi 0.35，Te 55.14），A 3（Ge 59.33，Bi 40 ，Te <40.17 和A 4（Ge 38.71，Bi 16.13，Te 45.16） ））由具有锗（Ge），铋（Bi）和碲（Te）的顶点的三角形组成图上的坐标表示。 掺杂的GeBiTe层含有杂质，其组成比在四个点（D 1（Ge 10 O 12，Bi 20 O，Te 70） （3），D 2（Ge 30 30，Bi 0，Te 70），D 3（Ge 70） ，Bi 2 O 3，Te 30 N）和D 4（Ge 50，Bi 20，Te 30 ））由三角形组成图上的坐标表示。