公开(公告)号：US20090206367A1

公开(公告)日：2009-08-20

申请号：US12031084

申请日：2008-02-14

Applicant: Robert J. Gauthier, JR. ,  Junjun Li ,  Souvick Mitra

Inventor： Robert J. Gauthier, JR. ,  Junjun Li ,  Souvick Mitra

IPC: H01L29/74 ,  H01L21/332

CPC classification number: H01L29/7436 ,  H01L27/0259 ,  H01L29/861

Abstract: A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a P+-N body diode and an N+-P body diode. The P+-N body diode and the N+-P body diode are laterally integrated.

Abstract translation: 设计结构体现在用于设计，制造或测试设计的机器可读介质中。 该设计结构包括一个P + -N体二极管和一个N + -P体二极管。 P + -N体二极管和N + -P体二极管横向集成。

公开(公告)号：US20090108289A1

公开(公告)日：2009-04-30

申请号：US11931517

申请日：2007-10-31

Applicant: Michel J. Abou-Khalil ,  Robert Gauthier ,  Hongmei Li ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam

Inventor： Michel J. Abou-Khalil ,  Robert Gauthier ,  Hongmei Li ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam

IPC: H01L27/06

CPC classification number: H01L27/0266 ,  H01L27/0259 ,  H01L27/0727 ,  H01L27/0817

Abstract: A design structure for a circuit providing the same trigger voltage across the multiple fingers is provided, which comprises a data representing an external current injection source connected to individual fingers of a multi-finger semiconductor device. For example, the external injection current is supplied to the body of a MOSFET or the gate of a thyristor. The magnitude of the supplied current from each external current injection source is adjusted so that each finger has the same trigger voltage. The external current supply circuit may comprise diodes or an RC triggered MOSFET. The components of the external current supply circuit may be tuned to achieve a desired predetermined trigger voltage across all fingers of the multi-finger semiconductor device.

Abstract translation: 提供了一种用于跨多个指状物提供相同触发电压的电路的设计结构，其包括表示连接到多指半导体器件的各个指状物的外部电流注入源的数据。 例如，外部注入电流被提供给MOSFET的主体或晶闸管的栅极。 调整来自每个外部电流注入源的供给电流的大小，使得每个手指具有相同的触发电压。 外部电流供应电路可以包括二极管或RC触发MOSFET。 可以调谐外部电流供应电路的组件以实现多指半导体器件的所有指状物上期望的预定触发电压。

公开(公告)号：US07518845B2

公开(公告)日：2009-04-14

申请号：US11422608

申请日：2006-06-07

Applicant: Robert J. Gauthier, Jr. ,  Dimitrios K. Kontos ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam

Inventor： Robert J. Gauthier, Jr. ,  Dimitrios K. Kontos ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam

IPC: H02H9/00 ,  H02H1/00

CPC classification number: H02H9/046

Abstract: An electrostatic discharge (ESD) power clamp circuit including a RC-delay element coupled to a plurality of serialized inverter elements with a power clamp element and an ESD-triggered keeper device coupled to the plurality of inverters. During negative mode ESD events, the ESD-triggered keeper device is activated and assists the power clamp element to pull up and strongly conduct current to protect the circuit. Additionally, a method of ESD protection in a circuit is provided. The method includes coupling a RC-delay element to an input of a plurality of serialized inverter elements, coupling an output of the plurality of serialized inverters with an ESD-triggered keeper device and a power clamp element, triggering the ESD-triggered keeper device to turn on during negative ESD events and conducting current by the power clamp element with assistance of the ESD-triggered keeper device to protect the circuit as a result of negative ESD events.

Abstract translation: 一种静电放电（ESD）功率钳位电路，其包括耦合到多个串联反相器元件的RC延迟元件，其具有耦合到所述多个逆变器的功率钳位元件和ESD触发的保持器装置。 在负模式ESD事件期间，ESD触发的保护装置被激活，并且帮助电源钳位元件上拉并强烈地传导电流以保护电路。 另外，提供了电路中ESD保护的方法。 该方法包括将RC延迟元件耦合到多个串联反相器元件的输入端，将多个串联反相器的输出与ESD触发的保持器装置和功率钳位元件耦合，将ESD触发的保持器装置触发 在ESD ESD事件期间接通电源，并通过ESD触发的保护装置的辅助，通过电源钳位元件传导电流，以保护电路由于负ESD事件。

公开(公告)号：US20090086391A1

公开(公告)日：2009-04-02

申请号：US11865820

申请日：2007-10-02

Applicant: Robert J. Gauthier, JR. ,  Junjun Li

Inventor： Robert J. Gauthier, JR. ,  Junjun Li

IPC: H02H9/00

CPC classification number: H01L27/0285

Abstract: An electronic discharge (ESD) protection circuit for protecting an integrated circuit chip from an ESD event. The ESD protection circuit includes a stack of BigFETs, a BigFET gate driver for driving the gates of the BigFETs and a triggering the BigFET gate driver to drive the gates of the BigFETs in response to an ESD event. The BigFET gate driver includes gate pull-up circuitry for pulling up the gate of a lower one of the BigFETs. The gate pull-up circuitry is configured so as to obviate the need for a diffusion contact between the stacked BigFETs, resulting in a significant savings in terms of the chip area needed to implement the ESD protection circuit.

Abstract translation: 一种用于保护集成电路芯片免受ESD事件的电子放电（ESD）保护电路。 ESD保护电路包括一叠BigFET，用于驱动BigFET栅极的BigFET栅极驱动器，以及响应于ESD事件触发BigFET栅极驱动器来驱动BigFET的栅极。 BigFET栅极驱动器包括用于拉低下一个BigFET的栅极的栅极上拉电路。 栅极上拉电路被配置为消除对堆叠的BigFET之间的扩散接触的需要，导致实现ESD保护电路所需的芯片面积的显着节省。

公开(公告)号：US20080308837A1

公开(公告)日：2008-12-18

申请号：US11762811

申请日：2007-06-14

Applicant: Robert J. Gauthier, JR. ,  Junjun Li ,  Souvick Mitra ,  Mahmoud A. Mousa ,  Christopher S. Putnam

Inventor： Robert J. Gauthier, JR. ,  Junjun Li ,  Souvick Mitra ,  Mahmoud A. Mousa ,  Christopher S. Putnam

IPC: H01L29/74 ,  H01L21/20 ,  H01L21/332 ,  H01L21/84 ,  H01L29/00

CPC classification number: H01L27/0262

Abstract: A Silicon on Insulator (SOI) Integrated Circuit (IC) chip with devices such as a vertical Silicon Controlled Rectifier (SCR), vertical bipolar transistors, a vertical capacitor, a resistor and/or a vertical pinch resistor and method of making the device(s). The devices are formed in a seed hole through the SOI surface layer and insulator layer to the substrate. A buried diffusion, e.g., N-type, is formed through the seed hole in the substrate. A doped epitaxial layer is formed on the buried diffusion and may include multiple doped layers, e.g., a P-type layer and an N-type layer. Polysilicon, e.g., P-type, may be formed on the doped epitaxial layer. Contacts to the buried diffusion are formed in a contact liner.

Abstract translation: 具有诸如垂直硅控制整流器（SCR），垂直双极晶体管，垂直电容器，电阻器和/或垂直钳位电阻器等器件的绝缘体硅（SOI）集成电路（IC）芯片及其制造方法 s）。 器件通过SOI表面层和绝缘体层形成在晶种孔中。 通过衬底中的种子孔形成例如N型的掩埋扩散。 掺杂的外延层形成在掩埋扩散层上，并且可以包括多个掺杂层，例如P型层和N型层。 可以在掺杂的外延层上形成多晶硅，例如P型。 与埋入扩散部的接触形成在接触衬里中。

公开(公告)号：US20080145993A1

公开(公告)日：2008-06-19

申请号：US12036319

申请日：2008-02-25

Applicant: Robert J. Gauthier ,  Junjun Li ,  Souvick Mitra ,  Mahmoud A. Mousa ,  Christopher Stephen Putnam

Inventor： Robert J. Gauthier ,  Junjun Li ,  Souvick Mitra ,  Mahmoud A. Mousa ,  Christopher Stephen Putnam

IPC: H01L21/8228

CPC classification number: H01L29/7436 ,  H01L21/84 ,  H01L27/0262 ,  H01L27/1203

Abstract: A silicon control rectifier, a method of making the silicon control rectifier and the use of the silicon control rectifier as an electrostatic discharge protection device of an integrated circuit. The silicon control rectifier includes a silicon body formed in a silicon layer in direct physical contact with a buried oxide layer of a silicon-on-insulator substrate, a top surface of the silicon layer defining a horizontal plane; and an anode of the silicon control rectifier formed in a first region of the silicon body and a cathode of the silicon control rectifier formed in an opposite second region of the silicon body, wherein a path of current flow between the anode and the cathode is only in a single horizontal direction parallel to the horizontal plane.

Abstract translation: 硅控制整流器，制造硅控制整流器的方法和使用硅控制整流器作为集成电路的静电放电保护器件。 硅控制整流器包括形成在硅层中的硅体，其与绝缘体上硅衬底的掩埋氧化物层直接物理接触，硅层的顶表面限定水平面; 并且形成在硅体的第一区域中的硅控制整流器的阳极和形成在硅体的相对的第二区域中的硅控制整流器的阴极，其中阳极和阴极之间的电流路径仅为 在平行于水平面的单个水平方向上。

公开(公告)号：US20080050880A1

公开(公告)日：2008-02-28

申请号：US11931634

申请日：2007-10-31

Applicant: Michel Abou-Khalil ,  Robert Gauthier ,  Hongmei Li ,  Junjun Li ,  Souvick Mitra ,  Christopher Putnam

Inventor： Michel Abou-Khalil ,  Robert Gauthier ,  Hongmei Li ,  Junjun Li ,  Souvick Mitra ,  Christopher Putnam

IPC: H01L21/336

CPC classification number: H01L29/6659 ,  H01L29/41733 ,  H01L29/41775 ,  H01L29/458 ,  H01L29/6653 ,  H01L29/7833 ,  H01L29/78621 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides a method in which a low-resistance connection between the MOS channel and silicided source/drain regions is provided that has an independence from the extension ion implant process as well as device overlap capacitance. The method of the present invention broadly includes selectively removing outer spacers of an MOS structure and then selectively plating a metallic or intermetallic material on exposed portions of a semiconductor substrate that were previously protected by the outer spacers. The present invention also provides a semiconductor structure that is formed utilizing the method. The semiconductor structure includes a low-resistance connection between the silicided source/drain regions and the channel regions which includes a selectively plated metallic or intermetallic material.

Abstract translation: 本发明提供了一种方法，其中提供了与扩展离子注入工艺无关的MOS沟道和硅化源极/漏极区之间的低电阻连接以及器件重叠电容。 本发明的方法广泛地包括选择性地去除MOS结构的外部间隔物，然后在先前由外部间隔物保护的半导体衬底的暴露部分上选择性地镀覆金属或金属间化合物。 本发明还提供了利用该方法形成的半导体结构。 半导体结构包括硅化源/漏区和沟道区之间的低电阻连接，其包括选择性镀金属或金属间化合物。

公开(公告)号：US20070262345A1

公开(公告)日：2007-11-15

申请号：US11781370

申请日：2007-07-23

Applicant: Robert Gauthier ,  Junjun Li ,  Souvick Mitra ,  Mahmoud Mousa ,  Christopher Putnam

Inventor： Robert Gauthier ,  Junjun Li ,  Souvick Mitra ,  Mahmoud Mousa ,  Christopher Putnam

IPC: H01L21/02 ,  H01L29/66

CPC classification number: H01L29/7436 ,  H01L21/84 ,  H01L27/0262 ,  H01L27/1203

Abstract: A silicon control rectifier, a method of making the silicon control rectifier and the use of the silicon control rectifier as an electrostatic discharge protection device of an integrated circuit. The silicon control rectifier includes a silicon body formed in a silicon layer in direct physical contact with a buried oxide layer of a silicon-on-insulator substrate, a top surface of the silicon layer defining a horizontal plane; and an anode of the silicon control rectifier formed in a first region of the silicon body and a cathode of the silicon control rectifier formed in an opposite second region of the silicon body, wherein a path of current flow between the anode and the cathode is only in a single horizontal direction parallel to the horizontal plane.

Abstract translation: 硅控制整流器，制造硅控制整流器的方法和使用硅控制整流器作为集成电路的静电放电保护器件。 硅控制整流器包括形成在硅层中的硅体，其与绝缘体上硅衬底的掩埋氧化物层直接物理接触，硅层的顶表面限定水平面; 并且形成在硅体的第一区域中的硅控制整流器的阳极和形成在硅体的相对的第二区域中的硅控制整流器的阴极，其中阳极和阴极之间的电流路径仅为 在平行于水平面的单个水平方向上。

公开(公告)号：US20070201173A1

公开(公告)日：2007-08-30

申请号：US11276411

申请日：2006-02-28

Applicant: Albert Chu ,  Robert Gauthier ,  Junjun Li ,  Thomas Wyckoff

Inventor： Albert Chu ,  Robert Gauthier ,  Junjun Li ,  Thomas Wyckoff

IPC: H02H9/00

CPC classification number: H01L27/0266

Abstract: An apparatus for protecting an integrated circuit from electrostatic discharge (ESD) includes an RC trigger device configured between a pair of power rails, a first control path coupled to the RC trigger device, and a second control path coupled to the RC trigger device. A power clamp is configured between the power rails for discharging current from an ESD event, the power clamp having an input coupled to outputs of the first and second control paths, the power clamp independently controllable by the first and second control paths. The first and second control paths are further configured to prevent the power clamp from reactivating following an initial deactivation of the power clamp.

Abstract translation: 用于保护集成电路免受静电放电（ESD）的装置包括RC触发装置，其配置在耦合到RC触发装置的一对电源轨，第一控制路径和耦合到RC触发装置的第二控制路径之间。 功率钳被配置在用于从ESD事件放电的电源轨之间，功率钳具有耦合到第一和第二控制路径的输出的输入，功率钳由第一和第二控制路径独立地控制。 第一和第二控制路径还被配置为防止在电源钳的初始去激活之后电源钳位被重新激活。

公开(公告)号：US20070170512A1

公开(公告)日：2007-07-26

申请号：US11275638

申请日：2006-01-20

Applicant: Robert Gauthier, Jr. ,  Junjun Li ,  Souvick Mitra ,  Mahmoud Mousa ,  Christopher Putnam

Inventor： Robert Gauthier, Jr. ,  Junjun Li ,  Souvick Mitra ,  Mahmoud Mousa ,  Christopher Putnam

IPC: H01L23/62

CPC classification number: H01L29/7436 ,  H01L21/84 ,  H01L27/0262 ,  H01L27/1203

Abstract: Disclosed are a silicon control rectifier, a method of making the silicon control rectifier and the use of the silicon control rectifier as an electrostatic discharge protection device of an integrated circuit. The silicon control rectifier includes a silicon body formed in a silicon layer in direct physical contact with a buried oxide layer of a silicon-on-insulator substrate, a top surface of the silicon layer defining a horizontal plane; and an anode of the silicon control rectifier formed in a first region of the silicon body and a cathode of the silicon control rectifier formed in an opposite second region of the silicon body, wherein a path of current flow between the anode and the cathode is only in a single horizontal direction parallel to the horizontal plane.

Abstract translation: 公开了一种硅控制整流器，制造硅控制整流器的方法和使用硅控整流器作为集成电路的静电放电保护器件。 硅控制整流器包括形成在硅层中的硅体，其与绝缘体上硅衬底的掩埋氧化物层直接物理接触，硅层的顶表面限定水平面; 并且形成在硅体的第一区域中的硅控制整流器的阳极和形成在硅体的相对的第二区域中的硅控制整流器的阴极，其中阳极和阴极之间的电流路径仅为 在平行于水平面的单个水平方向上。