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公开(公告)号：US11706014B1
公开(公告)日：2023-07-18
申请号：US17579630
申请日：2022-01-20
发明人： Natan Manevich , Dotan David Levi , Wojciech Wasko , Ariel Almog , Bar Shapira
IPC分类号： H04L7/00
CPC分类号： H04L7/0012
摘要： In one embodiment, a synchronized communication system includes a plurality of compute nodes, and clock connections to connect the compute nodes in a closed loop configuration, wherein the compute nodes are configured to distribute among the compute nodes a master clock frequency from any selected one of the compute nodes.
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公开(公告)号：US11693804B2
公开(公告)日：2023-07-04
申请号：US17338131
申请日：2021-06-03
发明人： Alex Rosenbaum , Oren Duer , Alexander Mikheev , Nitzan Carmi , Haggai Eran
IPC分类号： G06F13/00 , G06F13/40 , G06F15/173 , G06F13/16 , G06F13/42
CPC分类号： G06F13/4022 , G06F13/1673 , G06F13/4221 , G06F15/17331
摘要： A computerized system for efficient interaction between a host, the host having a first operating system, and a second operating system, the system comprising a subsystem on the second operating system which extracts data, directly from a buffer which is local to the host, wherein the system is operative for mapping memory from one bus associated with the first operating system to a different bus, associated with the second operating system and from which different bus the memory is accessed, thereby to emulate a connection between the first and second operating systems by cross-bus memory mapping.
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公开(公告)号：US20230208517A1
公开(公告)日：2023-06-29
申请号：US17568441
申请日：2022-01-04
发明人： Paraskevas Bakopoulos , Elad Mentovich , Tali Septon , Dimitrios Syrivelis , Ioannis (Giannis) Patronas , Dimitrios Kalavrouziotis , Moshe Oron
IPC分类号： H04B10/11
CPC分类号： H04B10/11
摘要： An apparatus comprises a support structure and one or more first optical components on the support structure that communicatively couple with a first endpoint. The one or more first optical components are configured to output and receive optical signals that travel over a free space medium to establish a secure link between the first endpoint and a second endpoint.
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公开(公告)号：US11683266B2
公开(公告)日：2023-06-20
申请号：US17963216
申请日：2022-10-11
发明人： Boris Pismenny , Miriam Menes , Idan Burstein , Liran Liss , Noam Bloch , Ariel Shahar
IPC分类号： H04L45/00 , H04L45/42 , G06F11/10 , H04L69/163 , H04L69/22
CPC分类号： H04L45/566 , G06F11/1004 , H04L45/38 , H04L45/42 , H04L69/163 , H04L69/22
摘要： A system includes a host processor, which has a host memory and is coupled to store data in a non-volatile memory in accordance with a storage protocol. A network interface controller (NIC) receives data packets conveyed over a packet communication network from peer computers containing, in payloads of the data packets, data records that encode data in accordance with the storage protocol for storage in the non-volatile memory. The NIC processes the data records in the data packets that are received in order in each flow from a peer computer and extracts and writes the data to the host memory, and when a data packet arrives out of order, writes the data packet to the host memory without extracting the data and processes the data packets in the flow so as to recover context information for use in processing the data records in subsequent data packets in the flow.
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公开(公告)号：US20230185600A1
公开(公告)日：2023-06-15
申请号：US17549949
申请日：2021-12-14
发明人： Wojciech Wasko , Dotan David Levi , Liron Mula , Natan Manevich
CPC分类号： G06F9/4825 , G06F9/485 , G06F13/1689 , G06F1/08
摘要： In one embodiment, a system includes a memory, a processing device including a device processor; and a device clock, and a peripheral device including an interface to share data with the processing device, a hardware clock, and processing circuitry to write respective interrupt signaling messages to the memory responsively to respective hardware clock values of the hardware clock, and wherein the device processor is configured, responsively to the respective interrupt signaling messages being written to the memory, to perform a time-dependent action.
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公开(公告)号：US11658803B2
公开(公告)日：2023-05-23
申请号：US17198889
申请日：2021-03-11
发明人： Boris Pismenny , Liran Liss , Ilya Lesokhin
CPC分类号： H04L9/0637 , H04L9/32 , H04L9/3242
摘要： A method, apparatus, and computer program product for processing a data record including encrypted and decrypted data is described. Various embodiments include receiving a data record including ciphertext and plaintext blocks and determining whether each block in the data record is a ciphertext block or a plaintext block. If a block is a ciphertext block, the ciphertext block is stored into a ciphertext record, decrypted into a plaintext block utilizing a decryption algorithm, and stored in a plaintext record. If the block is a plaintext block, the plaintext block is stored into the plaintext record, encrypted into a ciphertext block utilizing an encryption algorithm, and stored in the ciphertext record. Embodiments described also include authenticating the data record by passing each block of the ciphertext record to an authentication scheme and outputting the plaintext record to a destination application.
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公开(公告)号：US20230141761A1
公开(公告)日：2023-05-11
申请号：US18090538
申请日：2022-12-29
发明人： Or Gerlitz , Noam Bloch , Gal Yefet
IPC分类号： H04L67/104 , H04L43/062 , H04L43/0894 , H04L67/00 , H04L67/01
CPC分类号： H04L67/1044 , H04L43/062 , H04L43/0894 , H04L67/01 , H04L67/34
摘要： A network device includes a network interface, a host interface, and processing circuitry. The network interface is configured to connect to a communication network. The host interface is configured to connect to a host comprising a host processor running a client process. The processing circuitry is configured to receive packets belonging to a message having a message length, the message originating from a peer process, to identify, in at least some of the received packets, application-level information specifying the message length, to determine, based on the identified message length, that the packets of the message already received comprise only a portion of the message, and in response to determining that the client process benefits from receiving less than the entire message, to initiate reporting the packets of the message already received to the client process.
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98.发明申请公开(公告)号：US20230121874A1
公开(公告)日：2023-04-20
申请号：US17519411
申请日：2021-11-04
发明人： Paraskevas Bakopoulos , Ioannis Giannis Patronas , Dimitris Kalavrouziotis , Juan Jose Vegas Olmos , Elad Mentovich , Nikos Argyris
摘要： The disclosure addresses the problem of increased optical insertion losses in integrated optical switches. It enables the implementation of an array of optical amplifiers, typically with low/moderate gain, to compensate for optical insertion losses in the integrated switches. The amplifier is based on a doped optical fiber which is optically pumped by a pump laser. The integrated optical switch includes a transposer that facilitates connectivity between a set of fibers and a photonic chip through an optical mode conversion. An all passive circuitry is built in a doped fiber amplifier, WDM couplers combine/separate the signals from the pump, and splitters allow sharing of a single pump by multiple amplifiers. In addition, switch pigtails are implemented with the doped fiber.
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公开(公告)号：US11630369B2
公开(公告)日：2023-04-18
申请号：US17405101
申请日：2021-08-18
摘要： Embodiments are disclosed for generating an optical Pulse Amplitude Modulation 4-level (PAM-4) signal from bandwidth-limited duobinary electrical signals in a Mach-Zehnder modulator. An example system includes an MZM structure that comprises a first waveguide interferometer arm structure associated with a first semiconductor device and a second waveguide interferometer arm structure associated with a second semiconductor device. A polybinary electrical signal is applied to or between the first semiconductor device and the second semiconductor device to convert an input optical signal provided to the MZM structure into an optical PAM-4 signal.
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公开(公告)号：US11630274B2
公开(公告)日：2023-04-18
申请号：US17315312
申请日：2021-05-09
摘要： A network device includes an enclosure, a multi-chip module (MCM), an optical-to-optical connector, and a multi-core fiber (MCF) interconnect. The enclosure has a panel. The MCM is inside the enclosure. The optical-to-optical connector, which is mounted on the panel of the enclosure, is configured to transfer a plurality of optical communication signals. The MCF interconnect includes multiple fiber cores for routing the plurality of optical communication signals between the MCM and the panel. The MCF has a first end at which the multiple fiber cores are coupled to the MCM, and a second end at which the multiple fiber cores are connected to the optical-to-optical connector on the panel.
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