公开(公告)号：US09699084B1

公开(公告)日：2017-07-04

申请号：US14634847

申请日：2015-03-01

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark ,  Stuart C. Wray

IPC: H04L12/741 ,  H04L12/947 ,  H04L12/931

CPC classification number: H04L45/745 ,  H04L45/54 ,  H04L49/25 ,  H04L49/35

Abstract: A Software-Defined Networking (SDN) switch that includes external network ports for receiving external network traffic onto the SDN switch, external network ports for transmitting external network traffic out of the SDN switch, a Network Flow Switch (NFX) integrated circuit that has multiple network ports and that maintains a flow table, another NFX integrated circuit that has multiple network ports and that maintains a flow table, and a Network Flow Processor (NFP) circuit that maintains a flow table. The NFP circuit couples directly to a network port of the first NFX integrated circuit but does not couple directly to any network port of the second NFX integrated circuit. The NFP circuit sends a flow entry to one NFX integrated circuit along with an addressing label and the NFX integrated circuit uses the addressing label to determine that the flow entry is to be forwarded to the second NFX integrated circuit.

公开(公告)号：US09515946B2

公开(公告)日：2016-12-06

申请号：US14321756

申请日：2014-07-01

Applicant: Netronome Systems, Inc.

Inventor： Joseph M. Lamb

IPC: H04L12/28 ,  H04L12/863

CPC classification number: H04L47/622

Abstract: Incoming frame data is stored in a plurality of dual linked lists of buffers in a pipelined memory. The dual linked lists of buffers are maintained by a link manager. The link manager maintains, for each dual linked list of buffers, a first head pointer, a second head pointer, a first tail pointer, a second tail pointer, a head pointer active bit, and a tail pointer active bit. The first head and tail pointers are used to maintain the first linked list of the dual linked list. The second head and tail pointers are used to maintain the second linked list of the dual linked list. Due to the pipelined nature of the memory, the dual linked list system can be popped to supply dequeued values at a sustained rate of more than one value per the read access latency time of the pipelined memory.

Abstract translation: 输入帧数据被存储在流水线存储器中的多个缓冲器的双链表中。 缓冲区的双链表由链接管理器维护。 链路管理器针对缓冲器的每个双链表维护第一头指针，第二头指针，第一尾指针，第二尾指针，头指针活动位和尾指针有效位。 第一个头和尾指针用于维护双链表的第一个链表。 第二个头尾指针用于维护双链表的第二个链表。 由于存储器的流水线性质，可以弹出双链表系统以便以流水线存储器的读取访问等待时间为单位以多于一个值的持续速率提供出队值。

公开(公告)号：US09489337B2

公开(公告)日：2016-11-08

申请号：US14251592

申请日：2014-04-12

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark

IPC: G06F15/80 ,  G06F9/50 ,  G06F9/48 ,  G06F9/38 ,  G06F9/30 ,  G06F1/32

CPC classification number: G06F15/80 ,  G06F1/3237 ,  G06F1/3275 ,  G06F1/3287 ,  G06F9/30047 ,  G06F9/30076 ,  G06F9/38 ,  G06F9/3802 ,  G06F9/3877 ,  G06F9/3885 ,  G06F9/4843 ,  G06F9/5027 ,  G06F9/5038 ,  G06F15/8007 ,  G06F15/8046 ,  G06F15/8053 ,  Y02D10/128 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/171 ,  Y02D10/22

Abstract: A general purpose PicoEngine Multi-Processor (PEMP) includes a hierarchically organized pool of small specialized picoengine processors and associated memories. A stream of data input values is received onto the PEMP. Each input data value is characterized, and from the characterization a task is determined. Picoengines are selected in a sequence. When the next picoengine in the sequence is available, it is then given the input data value along with an associated task assignment. The picoengine then performs the task. An output picoengine selector selects picoengines in the same sequence. If the next picoengine indicates that it has completed its assigned task, then the output value from the selected picoengine is output from the PEMP. By changing the sequence used, more or less of the processing power and memory resources of the pool is brought to bear on the incoming data stream. The PEMP automatically disables unused picoengines and memories.

Abstract translation: 通用PicoEngine多处理器（PEMP）包括一个分层组织的小型专用微型引擎处理器和相关存储器的池。 数据输入值流被接收到PEMP上。 每个输入数据值被表征，并且从表征确定任务。 Picoengines按顺序选择。 当序列中的下一个微型引擎可用时，然后给出输入数据值以及相关的任务分配。 picoengine然后执行任务。 输出微型引擎选择器以相同的顺序选择微型引线。 如果下一个微微引擎指示它已经完成其分配的任务，则从PEMP输出所选择的微微引擎的输出值。 通过改变所使用的顺序，或多或少地将该池的处理能力和存储器资源承担在输入数据流上。 PEMP自动禁用未使用的打印机和内存。

公开(公告)号：US09467378B1

公开(公告)日：2016-10-11

申请号：US14634849

申请日：2015-03-01

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark ,  Stuart C. Wray

IPC: H04L12/28 ,  H04L12/741 ,  H04L12/947 ,  H04L12/931

CPC classification number: H04L45/745 ,  H04L45/54 ,  H04L49/25 ,  H04L49/35

Abstract: A method involving a Software-Defined Networking (SDN) switch. A packet is received onto a SDN switch via a NFX circuit. The NFX circuit determines that the packet matches no flow entry stored in any flow table in the NFX circuit and forwards the packet to a NFP circuit. The NFP circuit determines that the packet matches a first flow entry that applies to a relatively broad flow of packets stored in a flow table in the NFP circuit, generates a new flow entry that applies to a relatively narrow subflow of packets, and forwards the new flow entry to the NFX circuit that stores the new flow entry in a flow table in the NFX circuit. A subsequent packet is received onto the SDN switch via the NFX circuit and is switched using the new flow entry stored in the NFX circuit without forwarding the packet to the NFP circuit.

Abstract translation: 一种涉及软件定义网络（SDN）交换机的方法。 通过NFX电路将数据包接收到SDN交换机上。 NFX电路确定该分组与NFX电路中任何流表中存储的流条目匹配，并将数据包转发到NFP电路。 NFP电路确定该分组与适用于存储在NFP电路中的流表中的相对广泛的分组流的第一流条目匹配，生成适用于相对窄的分组子流的新流入口，并转发新的 流入NFX电路，将新流入口存储在NFX电路的流表中。 随后的数据包经由NFX电路接收到SDN交换机上，并使用存储在NFX电路中的新流程进行切换，而不将数据包转发到NFP电路。

公开(公告)号：US09450890B2

公开(公告)日：2016-09-20

申请号：US13941484

申请日：2013-07-13

Applicant: Netronome Systems, Inc.

Inventor： Chirag P. Patel ,  Gavin J. Stark

IPC: H04L12/931

CPC classification number: H04L49/20

Abstract: An egress packet modifier includes a script parser and a pipeline of processing stages. Rather than performing egress modifications using a processor that fetches and decodes and executes instructions in a classic processor fashion, and rather than storing a packet in memory and reading it out and modifying it and writing it back, the packet modifier pipeline processes the packet by passing parts of the packet through the pipeline. A processor identifies particular egress modifications to be performed by placing a script code at the beginning of the packet. The script parser then uses the code to identify a specific script of opcodes, where each opcode defines a modification. As a part passes through a stage, the stage can carry out the modification of such an opcode. As realized using current semiconductor fabrication process, the packet modifier can modify 200M packets/second at a sustained rate of up to 100 gigabits/second.

Abstract translation: 出口分组修饰符包括脚本解析器和处理阶段的流水线。 而不是使用处理器执行出口修改，处理器以经典处理器的方式获取和解码并执行指令，而不是将数据包存储在存储器中并将其读出并修改它并将其写回来，数据包修改器流水线通过传递来处理数据包 部分数据包通过管道。 处理器通过将脚本代码放置在分组的开始处来识别要执行的特定出口修改。 脚本解析器然后使用代码来识别操作码的特定脚本，其中每个操作码定义了一个修改。 作为一个阶段，舞台可以进行这样一个操作码的修改。 通过使用当前的半导体制造工艺实现，分组修改器可以以高达100吉比特/秒的持续速率修改200M分组/秒。

公开(公告)号：US09417844B2

公开(公告)日：2016-08-16

申请号：US14037312

申请日：2013-09-25

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark

IPC: G06F7/58

CPC classification number: G06F7/584

Abstract: A Self-Timed Logic Entropy Bit Stream Generator (STLEBSG) outputs a bit stream having non-deterministic entropy. The bit stream is supplied onto an input of a signal storage ring so that entropy of the bit stream is then stored in the ring as the bit stream circulates in the ring. Depending on the configuration of the ring, the bit stream as it circulates undergoes permutations, but the signal storage ring nonetheless stores the entropy of the injected bit stream. In one example, the STLEBSG is disabled and the bit stream is no longer supplied to the ring, but the ring continues to circulate and stores entropy of the original bit stream. With the STLEBSG disabled, a signal output from the ring is used to generate one or more random numbers.

Abstract translation: 自定时逻辑熵比特流发生器（STLEBSG）输出具有非确定性熵的比特流。 比特流被提供到信号存储环的输入端，使得当比特流在环中循环时，比特流的熵随后被存储在环中。 根据环的配置，其循环中的位流经历置换，但是信号存储环仍然存储注入的比特流的熵。 在一个示例中，STLEBSG被禁用并且比特流不再被提供给环，但是环继续循环并存储原始比特流的熵。 禁用STLEBSG时，使用来自环的信号输出来产生一个或多个随机数。

公开(公告)号：US09401880B1

公开(公告)日：2016-07-26

申请号：US14588084

申请日：2014-12-31

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark ,  Steven W. Zagorianakos ,  Ron L. Swartzentruber ,  Richard P. Bouley

IPC: H04L12/54 ,  G06F15/80 ,  H04L12/861 ,  H04L12/933 ,  H04L12/801

CPC classification number: H04L49/9047 ,  H04L47/13 ,  H04L49/102 ,  H04L49/9084

Abstract: An island-based network flow processor (IB-NFP) integrated circuit includes islands organized in rows. A configurable mesh event bus extends through the islands and is configured to form a local event ring. The configurable mesh event bus is configured with configuration information received via a configurable mesh control bus. The local event ring involves event ring circuits and event ring segments. In one example, a packet is received onto a first island. If an amount of a processing resource (for example, memory buffer space) available to the first island is below a threshold, then an event packet is communicated from the first island to a second island via the local event ring. In response, the second island causes a third island to communicate via a command/push/pull data bus with the first island, thereby increasing the amount of the processing resource available to the first island for handing incoming packets.

公开(公告)号：US09389908B1

公开(公告)日：2016-07-12

申请号：US14588280

申请日：2014-12-31

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark

IPC: G06F12/08 ,  G06F9/46 ,  G06F12/02

CPC classification number: G06F9/467 ,  G06F9/34 ,  G06F12/023 ,  G06F12/08 ,  G06F2212/251

Abstract: A transactional memory (TM) receives a lookup command across a bus from a processor. The command includes a memory address. In response to the command, the TM pulls an input value (IV). The memory address is used to read a word containing multiple result values (RVs), multiple reference values, and multiple mask values from memory. A selecting circuit within the TM uses a starting bit position and a mask size to select a portion of the IV. The portion of the IV is a lookup key value (LKV). The LKV is masked by each mask value thereby generating multiple masked values. Each masked value is compared to a reference value thereby generating multiple comparison values. A lookup table generates a selector value based upon the comparison values. A result value is selected based on the selector value. The selected result value is then communicated to the processor via the bus.

公开(公告)号：US09319333B2

公开(公告)日：2016-04-19

申请号：US14205824

申请日：2014-03-12

Applicant: Netronome Systems, Inc.

Inventor： Ron Lamar Swartzentruber

IPC: H04L12/801 ,  H04L12/54 ,  H04L12/24 ,  H04L12/823 ,  H04L12/863

CPC classification number: H04L47/326 ,  H04L47/29 ,  H04L47/30 ,  H04L47/54

Abstract: A device that receives a packet descriptor and a queue number that indicates a queue stored within a memory unit, and in response determines an instantaneous queue depth of the queue. The instantaneous queue depth is used to determine a drop probability. The drop probability is used to randomly determine if the packet descriptor should be stored in the queue. The queue has a first queue depth range and a second queue depth range that do not overlap. A first drop probability is associated with the first queue depth range and a second drop probability is associated with the second queue depth range. The first drop probability is used when the queue depth is within the first queue depth range. The second drop probability is used with the queue depth is within the second queue depth range. The device includes a random value generator and a drop indicator generator.

Abstract translation: 接收分组描述符的设备和指示存储在存储器单元中的队列的队列号，并且作为响应确定队列的瞬时队列深度。 瞬时队列深度用于确定丢弃概率。 丢弃概率用于随机确定包描述符是否应该存储在队列中。 队列具有不重叠的第一队列深度范围和第二队列深度范围。 第一丢弃概率与第一队列深度范围相关联，并且第二丢弃概率与第二队列深度范围相关联。 当队列深度在第一队列深度范围内时，使用第一个丢弃概率。 第二个丢弃概率用于队列深度在第二个队列深度范围内。 该装置包括随机值发生器和下降指示器发生器。

公开(公告)号：US20160099882A1

公开(公告)日：2016-04-07

申请号：US14507652

申请日：2014-10-06

Applicant: Netronome Systems, Inc.

Inventor： Ron Lamar Swartzentruber

IPC: H04L12/823 ,  H04L12/865

CPC classification number: H04L47/326 ,  H04L47/6275 ,  H04L49/00

Abstract: A method for receiving a packet descriptor associated with a packet and a queue number indicating a queue stored within a memory unit, determining a priority level of the packet and an amount of free memory available in the memory unit. Applying a global drop probability to generate a global drop indicator and applying a queue drop probability to generate a queue drop indicator. The global drop probability is a function of the amount of free memory. The queue drop probability is a function of instantaneous queue depth or drop precedence value. The packet is transmitted whenever the priority level is high. When the priority level is low, the packet is transmitted when both the global drop indicator and the queue drop indicator are a logic low value. When the priority level is low, the packet is not transmitted when either drop indicator is a logic low value.

Abstract translation: 一种用于接收与分组相关联的分组描述符的方法和指示存储在存储器单元中的队列的队列号，确定分组的优先级和可用存储器单元中的可用内存量。 应用全局丢弃概率来生成全局丢弃指示符并应用队列丢弃概率来生成队列丢弃指示符。 全局丢弃概率是空闲内存量的函数。 队列丢弃概率是瞬时队列深度或丢弃优先级值的函数。 每当优先级高时，传输数据包。 当优先级低时，当全局丢弃指示符和队列丢弃指示符均为逻辑低值时，传输数据包。 当优先级低时，当任一个丢包指示符为逻辑低电平值时，该数据包不传输。