公开(公告)号：US20130247181A1

公开(公告)日：2013-09-19

申请号：US12322321

申请日：2009-01-29

Applicant: Suman Saraf ,  Sharad Agrawal ,  Pankaj Kumar

Inventor： Suman Saraf ,  Sharad Agrawal ,  Pankaj Kumar

IPC: G06F21/00

CPC classification number: G06F21/566

Abstract: A method of and system for protecting a computer system against denial-of-service attacks or other exploitation. The method comprises collecting network data and analyzing the network data using statistical and heuristic techniques to identify the source of the exploitation upon receiving an indication of exploitation. Upon identifying the network source, the network data associated with the network is blocked, redirected, or flow controlled. Preferably, the method also includes identifying when the system is being exploited.

Abstract translation: 一种用于保护计算机系统免遭拒绝服务攻击或其他开发的方法和系统。 该方法包括收集网络数据并使用统计和启发式技术分析网络数据，以便在接收到开发指示时识别开发的来源。 在识别网络源时，与网络相关联的网络数据被阻塞，重定向或流量控制。 优选地，该方法还包括识别系统什么时候被利用。

公开(公告)号：US20130185570A1

公开(公告)日：2013-07-18

申请号：US13785108

申请日：2013-03-05

Applicant: Pankaj Kumar ,  Hang T. Nguyen ,  Christopher Houghton ,  David A. Biermann

Inventor： Pankaj Kumar ,  Hang T. Nguyen ,  Christopher Houghton ,  David A. Biermann

IPC: G06F1/26

CPC classification number: G06F1/3296 ,  G05F1/46 ,  G06F1/26 ,  G06F1/3206 ,  G06F1/3228 ,  G06F1/324 ,  G06F9/3016 ,  Y02D10/126 ,  Y02D10/172

Abstract: In one embodiment, the present invention includes a processor having a plurality of cores and a control logic to control provision of a voltage/frequency to a first core of the plurality of cores independently of provision of a voltage/frequency to at least a second core of the plurality of cores. In some embodiments, the voltages may be provided from one or more internal voltage regulators of the processor. Other embodiments are described and claimed.

公开(公告)号：US08441281B2

公开(公告)日：2013-05-14

申请号：US13165500

申请日：2011-06-21

Applicant: Makeshwar Kothandaraman ,  Pankaj Kumar ,  Paul K. Hartley ,  John Christopher Kriz

Inventor： Makeshwar Kothandaraman ,  Pankaj Kumar ,  Paul K. Hartley ,  John Christopher Kriz

IPC: H03K19/003 ,  H03K19/094 ,  H03K19/0175

CPC classification number: H03K19/09432 ,  H03K19/018528

Abstract: A differential buffer circuit having increased output voltage swing includes a differential input stage including at least first and second transistors, the first and second transistors being operative to receive first and second signals, respectively. The buffer circuit further includes a bias stage connected between the differential input stage and a first voltage source. The bias stage is operative to generate a quiescent current as a function of a third signal supplied to the bias stage. A load circuit is connected between a second voltage source and the differential input stage, first and second differential outputs of the buffer circuit being generated at a junction between the load circuit and the differential input stage. The load circuit includes first and second switching elements coupled with the first and second transistors, respectively. The first switching element is operative to electrically connect the first differential output to the second voltage source when the first transistor is turned off. The second switching element is operative to electrically connect the second differential output to the second voltage source when the second transistor is turned off.

Abstract translation: 具有增加的输出电压摆幅的差分缓冲电路包括至少包括第一和第二晶体管的差分输入级，第一和第二晶体管分别用于接收第一和第二信号。 缓冲电路还包括连接在差分输入级与第一电压源之间的偏置级。 偏置级用于产生作为提供给偏置级的第三信号的函数的静态电流。 负载电路连接在第二电压源和差分输入级之间，缓冲电路的第一和第二差分输出在负载电路和差分输入级之间的结点处产生。 负载电路分别包括与第一和第二晶体管耦合的第一和第二开关元件。 当第一晶体管截止时，第一开关元件可操作以将第一差分输出电连接到第二电压源。 当第二晶体管截止时，第二开关元件可操作以将第二差分输出电连接到第二电压源。

公开(公告)号：US20130021085A1

公开(公告)日：2013-01-24

申请号：US13186310

申请日：2011-07-19

Applicant: Pankaj Kumar ,  Pramod Parameswaran ,  Makeshwar Kothandaraman

Inventor： Pankaj Kumar ,  Pramod Parameswaran ,  Makeshwar Kothandaraman

IPC: H03L5/00

CPC classification number: H03K3/356113

Abstract: A voltage level translator circuit for translating an input signal referenced to a first voltage supply to an output signal referenced to a second voltage supply includes an input stage for receiving the input signal, the input stage including at least first and second nodes, a voltage at the second node being a logical complement of a voltage at the first node. A load circuit is coupled with the input stage, the load circuit being operative to at least temporarily store a signal at the first and/or second nodes which is indicative of a logical state of the input signal. An output stage connected with the second node is operative to generate an output signal which is indicative of a logical state of the input signal. The voltage level translator circuit further includes a compensation circuit connected with the output stage and operative to balance pull-up and pull-down propagation delays in the voltage level translator circuit as a function of a voltage at the first node.

Abstract translation: 用于将参考第一电压源的输入信号转换为参考第二电压源的输出信号的电压电平转换器电路包括用于接收输入信号的输入级，输入级至少包括第一和第二节点， 第二节点是第一节点处的电压的逻辑补码。 负载电路与输入级耦合，负载电路可操作以至少临时存储指示输入信号的逻辑状态的第一和/或第二节点处的信号。 与第二节点连接的输出级可操作以产生指示输入信号的逻辑状态的输出信号。 电压电平转换器电路还包括与输出级连接的补偿电路，并且可操作以平衡电压电平转换器电路中的上拉和下拉传播延迟作为第一节点处的电压的函数。

公开(公告)号：US20130007573A1

公开(公告)日：2013-01-03

申请号：US13175500

申请日：2011-07-01

Applicant: Sivakumar Radhakrishnan ,  Mark A. Schmisseur ,  Sin S. Tan ,  Kenneth C. Haren ,  Thomas C. Brown ,  Pankaj Kumar ,  Vinodh Gopal ,  Wajdi K. Feghali

Inventor： Sivakumar Radhakrishnan ,  Mark A. Schmisseur ,  Sin S. Tan ,  Kenneth C. Haren ,  Thomas C. Brown ,  Pankaj Kumar ,  Vinodh Gopal ,  Wajdi K. Feghali

IPC: H03M13/09 ,  G06F11/10

CPC classification number: G06F11/10 ,  G06F11/1076 ,  H03M1/1052 ,  H03M7/42 ,  H03M13/09 ,  H03M13/091 ,  H03M13/158 ,  H03M13/6575

Abstract: Embodiments of the present disclosure describe methods, apparatus, and system configurations for cyclic redundancy check circuits using Galois-field arithmetic.

Abstract translation: 本公开的实施例描述了使用伽罗瓦域算术的循环冗余校验电路的方法，装置和系统配置。

公开(公告)号：US20120166909A1

公开(公告)日：2012-06-28

申请号：US12976247

申请日：2010-12-22

Applicant: Mark A. Schmisseur ,  Sivakumar Radhakrishnan ,  Pankaj Kumar ,  Marc A. Goldschmidt ,  Peter Molnar

Inventor： Mark A. Schmisseur ,  Sivakumar Radhakrishnan ,  Pankaj Kumar ,  Marc A. Goldschmidt ,  Peter Molnar

IPC: G11C29/00

CPC classification number: G06F11/1076

Abstract: A method and apparatus to enable data integrity checking of a block of data while the block of data is being transferred from a volatile memory to a non-volatile storage device is provided. The data integrity checking is performed in conjunction with Direct Memory Access operations and Redundant Array of Independent Disk (RAID) operations. In addition, data integrity checking of syndrome blocks in the RAID is performed during transfers to/from the storage devices in the RAID system and during RAID update and RAID data reconstruction operations.

Abstract translation: 提供了一种方法和装置，用于在数据块从易失性存储器传输到非易失性存储装置的同时使数据块的数据完整性检查得以实现。 数据完整性检查与直接内存访问操作和独立磁盘冗余阵列（RAID）操作一起执行。 此外，在向RAID系统的存储设备传输期间以及在RAID更新和RAID数据重建操作期间执行RAID中的校验块的数据完整性检查。

公开(公告)号：US08130030B2

公开(公告)日：2012-03-06

申请号：US12610276

申请日：2009-10-31

Applicant: Pankaj Kumar ,  Pramod Elamannu Parameswaran ,  Makeshwar Kothandaraman ,  Vani Deshpande ,  John Kriz

Inventor： Pankaj Kumar ,  Pramod Elamannu Parameswaran ,  Makeshwar Kothandaraman ,  Vani Deshpande ,  John Kriz

IPC: G05F1/10

CPC classification number: H03K17/693 ,  H03K19/00315 ,  H03K19/007

Abstract: A method includes controllably generating a first bias voltage from a supply voltage to be within an upper tolerable limit of an operating voltage of an IO receiver, and controllably generating a second bias voltage from an external voltage supplied through an IO pad to be within the upper tolerable limit of the operating voltage of the IO receiver. The method also includes deriving an output voltage from the first bias voltage during a normal condition and a tolerant condition, and deriving the output voltage from the second bias voltage during a failsafe condition. The tolerant condition is a mode of operation where the external voltage supplied through the IO pad varies from zero to a value higher than the supply voltage, and the failsafe condition is a mode of operation where the supply voltage is zero.

Abstract translation: 一种方法包括可控制地从电源电压产生第一偏置电压，使其在IO接收器的工作电压的上限允许极限内，并且可控制地从通过IO焊盘提供的外部电压产生第二偏置电压以在上部 IO接收器的工作电压允许限制。 该方法还包括在正常条件和容限条件期间从第一偏置电压导出输出电压，以及在故障安全状态期间从第二偏置电压导出输出电压。 容许条件是通过IO垫提供的外部电压从零变化到高于电源电压的值的操作模式，并且故障保护条件是电源电压为零的操作模式。

公开(公告)号：US08125267B2

公开(公告)日：2012-02-28

申请号：US12889440

申请日：2010-09-24

Applicant: Pankaj Kumar ,  Pramod E Parameswaran ,  Makeshwar Kothandaraman ,  Vani Deshpande ,  John Kriz

Inventor： Pankaj Kumar ,  Pramod E Parameswaran ,  Makeshwar Kothandaraman ,  Vani Deshpande ,  John Kriz

IPC: G05F1/10

CPC classification number: H03K19/00315

Abstract: A method includes controllably generating a first bias voltage from a supply voltage to be within an upper tolerable limit of an operating voltage of one or more constituent active circuit element(s) of an Input/Output (IO) core device of an integrated circuit (IC) to be interfaced with an IO pad, and controllably generating a second bias voltage from an external voltage supplied through the IO pad to be within the upper tolerable limit of the operating voltage of the one or more constituent active circuit element(s) of the IO core device to be interfaced with the IO pad. The method also includes controllably utilizing a control signal generated by the IO core to derive an output bias voltage from the first bias voltage during a driver mode of operation or the second bias voltage during a failsafe mode of operation and a tolerant mode of operation.

Abstract translation: 一种方法包括可控制地从电源电压产生第一偏置电压，使其处于集成电路的输入/输出（IO）核心器件的一个或多个构成的有源电路元件的工作电压的上容许限度内（ IC）与IO焊盘接口，并且可控制地从通过IO焊盘提供的外部电压产生第二偏置电压，使其在所述一个或多个构成的有源电路元件的工作电压的上容许限度内 要与IO接口连接的IO内核设备。 该方法还包括可控制地利用由IO核心产生的控制信号，以在驱动器操作模式期间从第一偏置电压导出输出偏置电压，或者在故障安全操作模式和容限操作模式期间导出第二偏置电压。

公开(公告)号：US20120024748A1

公开(公告)日：2012-02-02

申请号：US13260919

申请日：2010-03-29

Applicant: Saravanan Subramani ,  Debasis Bhattacharyya ,  Karthikeyani Arumugam Velayutham ,  Pankaj Kumar Kasliwal ,  Krishnan Venkatachalam

Inventor： Saravanan Subramani ,  Debasis Bhattacharyya ,  Karthikeyani Arumugam Velayutham ,  Pankaj Kumar Kasliwal ,  Krishnan Venkatachalam

IPC: C10G1/00 ,  C10G11/02

CPC classification number: C10G11/187 ,  B01J29/084 ,  B01J29/40 ,  B01J29/80 ,  B01J35/0006 ,  B01J2229/42 ,  C10G2300/202 ,  C10G2300/305 ,  C10G2300/701 ,  C10G2400/02

Abstract: The present invention relates to a fluidized catalytic cracking process for cracking hydrocarbon feed having organo-sulfur compound as an impurity, said process comprising: adding a heavy metal poisoned spent catalyst to an equilibrium catalyst to obtain a composite circulating catalyst, wherein the heavy metal poisoned spent catalyst is added in an amount to maintain the activity of the circulating catalyst; and obtaining a fluidized catalytic cracked product.The present invention further relates to fluidized catalytic cracked product obtained by the process of the present invention. The sulfur content of the fluidized catalytic cracked product mainly gasoline which is boiling in the range of C5-250° C. reduced by more than 20% (wt/wt). And Research Octane number of the fluidized catalytic cracked product is increased by more than 1 unit.

Abstract translation: 本发明涉及一种用于裂化具有有机硫化合物作为杂质的烃进料的流化催化裂化方法，所述方法包括：向沉淀催化剂中加入重金属中毒废催化剂以得到复合循环催化剂，其中重金属中毒 添加废催化剂以维持循环催化剂的活性; 得到流化催化裂化产物。 本发明还涉及通过本发明的方法获得的流化催化裂化产物。 主要是在C5-250℃范围内沸腾的汽油的流化催化裂化产物的硫含量降低了20％（wt / wt）。 研究表明，流化催化裂化产物的辛烷值增加了1个以上。

公开(公告)号：US20110205033A1

公开(公告)日：2011-08-25

申请号：US12934132

申请日：2009-03-26

Applicant: Lakshmi Kanta Bandyopadhyay ,  Swades Kumar Chaulya ,  Pankaj Kumar Mishra

Inventor： Lakshmi Kanta Bandyopadhyay ,  Swades Kumar Chaulya ,  Pankaj Kumar Mishra

IPC: H04Q5/22

CPC classification number: G01S5/0289 ,  E21F17/18

Abstract: The wireless information and safety system for mines of the present invention enables continuously tracking and monitoring underground miners and moveable equipment in underground mines using ZigBee-enabled active RFID devices forming a wireless network among them and other static and mobile ZigBee devices placed at strategic locations. The present invention provides a wireless information and safety system for mines comprises in combination of ZigBee-compliant devices (programmable to operate as end devices, routers and coordinators by hardware specific embedded software) and wireless sensor network (WSN) software having various application modules both for underground and opencast mines. Use of the system of the present invention would help in identifying the miners entering in underground mine to keep the track of the miners and maintain computerized attendance. This would help in monitoring equipment locations and their operation to improve productivity and reduce fatal collision accident. This would help in locating and tracking the miners in case of disaster for speedy rescue operation. This would help in monitoring miners' unsafe practice and providing warning to the respective miner. This would further help in real time monitoring environmental parameters in underground mine. This would also help in sending coded message to the concerned person in underground mine. This would further help in monitoring movement of dumpers in opencast mine, which will ultimately help in optimum shovel-dumper performance and improving productivity.

Abstract translation: 本发明的矿山无线信息和安全系统能够使用ZigBee启用的有源RFID设备在地下矿井中连续跟踪和监测地下矿工和移动设备，从而形成位于战略位置的其他静态和移动ZigBee设备之间的无线网络。 本发明提供了一种用于矿山的无线信息和安全系统，其包括符合ZigBee的设备（可编程以作为终端设备操作，通过硬件专用嵌入式软件的路由器和协调器）和具有各种应用模块的无线传感器网络（WSN）软件 用于地下和露天矿。 使用本发明的系统将有助于识别进入地下矿井的矿工，以保持矿工的轨道并保持电脑出勤。 这将有助于监测设备位置及其运行情况，以提高生产率并减少致命的碰撞事故。 这将有助于在发生灾难的情况下定位和跟踪矿工，以便迅速的救援行动。 这有助于监测矿工不安全的做法，并向相关矿工提供警告。 这将进一步有助于实时监测地下矿井的环境参数。 这也有助于向地下矿井的有关人员发送编码信息。 这将进一步有助于监测露天矿的翻斗车的运动，这将最终有助于最佳铲斗性能和提高生产率。