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    DC-DC buck circuit
    93.
    发明授权
    DC-DC buck circuit 有权
    DC-DC降压电路

    公开(公告)号：US09225246B2

    公开(公告)日：2015-12-29

    申请号：US14166010

    申请日：2014-01-28

    Applicant: Yu Ye Liu

    Inventor： Yu Ye Liu

    IPC: H02M3/156 ,  H02M3/158

    CPC classification number: H02M3/158 ,  H02M3/1588 ,  Y02B70/1466

    Abstract: A DC-DC Buck circuit has a DC input terminal, a DC output terminal, a ground terminal, an inductor, a capacitor, a sampling resistor, a PWM control chip and a DrMOS chip. The output of the driver pin of the PWM control chip is unrelated to the voltage between the inductor and the sampling resistor. The DC-DC Buck circuit can produce a larger output voltage while also being compatible with a DrMOS chip.

    Abstract translation: DC-DC降压电路具有直流输入端子，直流输出端子，接地端子，电感器，电容器，采样电阻器，PWM控制芯片和DrMOS芯片。 PWM控制芯片的驱动器引脚的输出与电感和采样电阻之间的电压无关。 DC-DC降压电路可以产生更大的输出电压，同时也与DrMOS芯片兼容。

    Decoupling sampling clock and error clock in a data eye
    97.
    发明授权
    Decoupling sampling clock and error clock in a data eye 有权
    在数据眼中去除采样时钟和错误时钟

    公开(公告)号：US08532240B2

    公开(公告)日：2013-09-10

    申请号：US12968538

    申请日：2011-01-03

    Applicant: Paul Tracy ,  Mohammad Mobin ,  Ye Liu ,  Lane A. Smith

    Inventor： Paul Tracy ,  Mohammad Mobin ,  Ye Liu ,  Lane A. Smith

    IPC: H04B1/10 ,  H04L7/02 ,  H03K5/159

    CPC classification number: H04L25/03038

    Abstract: In described embodiments, a transceiver includes an eye monitor, clock and data recovery, and adaptation modules. Data sampling clock phase and error clock phase determined from a data eye are decoupled in the transceiver during a sampling phase correction process. Decoupling these clock phases during the sampling phase correction process allows relative optimization of system equalization parameters without degradation of various adaptation algorithms. Such adaptation algorithms might be employed for received signal gain and equalization such as, for example, Decision Feedback Equalizer (DFE) adaptation. Deriving the data sampling clock and error clock phases from the same clock generation source and with independent clock control enables an iterative sampling phase correction process that allows for accelerated clock and data recovery (CDR) without disturbing the data eye shape.

    Abstract translation: 在所描述的实施例中，收发器包括眼睛监视器，时钟和数据恢复以及适配模块。 在采样相位校正过程中，从数据眼睛确定的数据采样时钟相位和误差时钟相位在收发器中解耦。 在采样相位校正过程中去耦合这些时钟相位允许系统均衡​​参数的相对优化，而不会降低各种自适应算法。 这样的适配算法可以用于接收信号增益和均衡，例如，判决反馈均衡器（DFE）适配。 从相同的时钟产生源和独立的时钟控制中获取数据采样时钟和错误时钟相位，可以实现迭代采样相位校正过程，可以在不影响数据眼睛形状的情况下加速时钟和数据恢复（CDR）。

    Method of Compensating for Nonlinearity in a DFE-based Receiver
    98.
    发明申请
    Method of Compensating for Nonlinearity in a DFE-based Receiver 有权
    在基于DFE的接收机中补偿非线性的方法

    公开(公告)号：US20130077669A1

    公开(公告)日：2013-03-28

    申请号：US13244985

    申请日：2011-09-26

    Applicant: Amaresh Malipatil ,  Mohammad Mobin ,  Pervez Aziz ,  Ye Liu

    Inventor： Amaresh Malipatil ,  Mohammad Mobin ,  Pervez Aziz ,  Ye Liu

    IPC: H04L27/01

    CPC classification number: H04L25/03019 ,  H04L2025/03681 ,  H04L2025/037

    Abstract: A receiver has an input and a decision feedback equalizer (DFE). The DFE couples to the receiver input and has at least one tap coefficient. An input signal, having a first amplitude level insufficient to cause significant non-linear distortion in the receiver, is applied to the receiver input. After the DFE adapts to the applied input signal having the first amplitude level by adjusting the at least one tap coefficient, the adaptation process is stopped. Then the at least one tap coefficient is scaled by a factor α and the amplitude of input signal is adjusted to a second amplitude level greater than the first amplitude level by the scale factor α. Although the second amplitude level might be sufficient to cause significant non-linear distortion in the receiver, the scaled tap coefficient has the correct values for proper DFE operation in the presence of the non-linear distortion.

    Abstract translation: 接收机具有输入和判决反馈均衡器（DFE）。 DFE耦合到接收器输入，并具有至少一个抽头系数。 具有不足以在接收机中引起显着的非线性失真的具有第一幅度电平的输入信号被施加到接收器输入端。 在DFE通过调整至少一个抽头系数来适应具有第一幅度电平的所施加的输入信号之后，停止适配处理。 然后，通过因子α对至少一个抽头系数进行缩放，并且将输入信号的幅度调整到大于第一幅度电平的比例因子α的第二幅度电平。 虽然第二幅度电平可能足以在接收机中引起显着的非线性失真，但是在存在非线性失真的情况下，经缩放的抽头系数具有适当的DFE操作的正确值。

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