公开(公告)号：US08352808B2

公开(公告)日：2013-01-08

申请号：US12573246

申请日：2009-10-05

Applicant: Yong June Kim ,  Jun Jin Kong ,  Jae Hong Kim ,  Kyoung Lae Cho

Inventor： Yong June Kim ,  Jun Jin Kong ,  Jae Hong Kim ,  Kyoung Lae Cho

IPC: G06F11/00 ,  G06F12/00

CPC classification number: G06F11/1008

Abstract: A data storage device receives write data and includes a controller configured to determine a characteristic of the write data and provide a first control signal in response to the determined characteristic, a randomizer configured to selectively randomize or not randomize the write data in response to the first control signal to thereby generate randomized write data, and a data storage unit configured to store the randomized write data.

Abstract translation: 数据存储装置接收写入数据，并且包括控制器，被配置为确定写入数据的特性并响应于所确定的特性提供第一控制信号;随机化器，被配置为响应于第一个数据，选择性地随机化或不使写入数据随机化 从而生成随机写入数据，以及数据存储单元，被配置为存储随机写入数据。

公开(公告)号：US08345487B2

公开(公告)日：2013-01-01

申请号：US12774814

申请日：2010-05-06

Applicant: Yong June Kim ,  Jae Hong Kim ,  Jun Jin Kong ,  Hong Rak Son ,  Seung-Hwan Song

Inventor： Yong June Kim ,  Jae Hong Kim ,  Jun Jin Kong ,  Hong Rak Son ,  Seung-Hwan Song

IPC: G11C11/413

CPC classification number: G11C11/5642 ,  G11C29/00 ,  G11C2211/5634

Abstract: A method setting a read voltage to minimize data read errors in a semiconductor memory device including multi-bit memory cells. In the method, a read voltage associated with a minimal number of read data error is set based on a statistic value of a voltage distribution corresponding to each one of a plurality of voltage states.

Abstract translation: 一种设置读取电压以最小化包括多位存储器单元的半导体存储器件中的数据读取错误的方法。 在该方法中，基于与多个电压状态中的每一个相对应的电压分布的统计值来设置与最小数量的读取数据错误相关联的读取电压。

公开(公告)号：US20120215963A1

公开(公告)日：2012-08-23

申请号：US13303512

申请日：2011-11-23

Applicant: Yong June KIM ,  Jung Soo CHUNG ,  Jun Jin KONG ,  Kyoung Lae CHO

Inventor： Yong June KIM ,  Jung Soo CHUNG ,  Jun Jin KONG ,  Kyoung Lae CHO

IPC: G06F12/00 ,  G06F12/02

CPC classification number: G06F13/16 ,  G11C7/1006

Abstract: A semiconductor memory system and a programming method performed by the same. The semiconductor memory system includes: a semiconductor memory device having a storage area; a memory controller for controlling programming and reading of the storage area of the semiconductor memory device; at least one first randomizer for changing program data to be programmed into the storage area to first random data by using a first sequence in a first period; and at least one second randomizer for changing the first random data to second random data by using a second sequence in a second period that is different from the first period.

Abstract translation: 半导体存储器系统及其编程方法。 半导体存储器系统包括：具有存储区域的半导体存储器件; 用于控制半导体存储器件的存储区域的编程和读取的存储器控​​制器; 至少一个第一随机化器，用于通过在第一周期中使用第一序列来将要被编程到所述存储区域中的程序数据改变为第一随机数据; 以及至少一个第二随机化器，用于通过在与第一周期不同的第二周期中使用第二序列来将第一随机数据改变为第二随机数据。

公开(公告)号：US08200607B2

公开(公告)日：2012-06-12

申请号：US12292539

申请日：2008-11-20

Applicant: Jae Hong Kim ,  Heeseok Eun ,  Yong June Kim ,  Jun Jin Kong ,  Seung-Hwan Song

Inventor： Jae Hong Kim ,  Heeseok Eun ,  Yong June Kim ,  Jun Jin Kong ,  Seung-Hwan Song

IPC: G06F17/00 ,  G06N5/02

CPC classification number: G06N99/005

Abstract: Disclosed are a memory device and a data decision method. The memory device may include a memory cell array, and a decision unit configured to read first data from the memory cell array via a first channel, perform at least one of a hard and soft decision on the first data using a first number of decision levels set based on characteristics of the first channel, read second data from the memory cell array via a second channel, and perform a soft decision on the second data using a second number of decision levels set based on characteristics of the second channel.

Abstract translation: 公开了一种存储器件和数据判定方法。 存储器装置可以包括存储单元阵列，以及判定单元，被配置为经由第一通道从存储单元阵列读取第一数据，使用第一数量的判定级别对第一数据执行硬判决和软判决中的至少一个 基于第一信道的特性设置，经由第二信道从存储器单元阵列读取第二数据，并且使用基于第二信道的特性设置的第二数量的判定级来对第二数据执行软判决。

公开(公告)号：US20110276857A1

公开(公告)日：2011-11-10

申请号：US13103460

申请日：2011-05-09

Applicant: Yong June Kim ,  Kyoung Lae Cho ,  Hong Rak Son

Inventor： Yong June Kim ,  Kyoung Lae Cho ,  Hong Rak Son

IPC: G06F12/00 ,  G06F11/10 ,  H03M13/05

CPC classification number: G06F11/1048 ,  G11C29/10 ,  G11C2029/0411 ,  H03M7/46

Abstract: A data storage device includes a non-volatile memory device including a plurality of memory cells and a memory controller. The memory controller is configured to modify an arrangement of program data and to program the modified program data into the plurality of memory cells. The memory controller modifies the program data to eliminate a given data pattern causing physical interference between adjacent memory cells from the modified program data.

Abstract translation: 数据存储装置包括包括多个存储器单元和存储器控制器的非易失性存储器件。 存储器控制器被配置为修改程序数据的布置并且将修改的程序数据编程到多个存储器单元中。 存储器控制器修改程序数据以消除给定的数据模式，从修改的程序数据导致相邻存储器单元之间的物理干扰。

公开(公告)号：US20110246853A1

公开(公告)日：2011-10-06

申请号：US13069834

申请日：2011-03-23

Applicant: Yong-June KIM ,  Jun-Jin Kong ,  Young-Hwan Lee ,  Jae-Hong Kim

Inventor： Yong-June KIM ,  Jun-Jin Kong ,  Young-Hwan Lee ,  Jae-Hong Kim

IPC: G06F11/08

CPC classification number: G06F11/1048

Abstract: An error control coding (ECC) circuit includes a first decoder, a second decoder, and a controller. The first decoder receives encoded data comprising a first parity and a second parity. The first decoder decodes the encoded data to a first code by using the first parity. The second decoder is connected to the first decoder. The second decoder is configured to decode the encoded data when the first decoder is deactivated and decode the first code using the second parity when the first decoder is deactivated. The controller transmits a control signal to the first decoder and the second decoder to control the first decoder and the second decoder.

Abstract translation: 错误控制编码（ECC）电路包括第一解码器，第二解码器和控制器。 第一解码器接收包括第一奇偶校验和第二奇偶校验的编码数据。 第一解码器通过使用第一奇偶校验将编码数据解码为第一代码。 第二解码器连接到第一解码器。 第二解码器被配置为当第一解码器被去激活时解码编码数据，并且当第一解码器被去激活时使用第二奇偶校验解码第一代码。 控制器向第一解码器和第二解码器发送控制信号以控制第一解码器和第二解码器。

公开(公告)号：US20110216598A1

公开(公告)日：2011-09-08

申请号：US13016063

申请日：2011-01-28

Applicant: Jaehong KIM ,  Kijun Lee ,  Yong June Kim ,  Heeseok Eun

Inventor： Jaehong KIM ,  Kijun Lee ,  Yong June Kim ,  Heeseok Eun

IPC: G11C16/26

CPC classification number: G11C16/3427 ,  G11C16/26

Abstract: Provided are a memory system and an operating method thereof. The operating method reads an observation memory cell at least one time with different read voltages to configure a first read data symbol, reads a plurality of interference memory cells adjacent to the observation memory cell at least one time with different read voltages to configure second read data symbols, and determines a logical value of the observation memory cell based on the first read data symbol and the second read data symbols.

Abstract translation: 提供了一种存储器系统及其操作方法。 操作方法用不同的读取电压至少一次读取观察存储器单元以配置第一读取数据符号，至少用不同的读取电压读取与观察存储器单元相邻的多个干扰存储器单元以配置第二读取数据 符号，并且基于第一读取数据符号和第二读取数据符号确定观察存储器单元的逻辑值。

公开(公告)号：US20110216590A1

公开(公告)日：2011-09-08

申请号：US13040626

申请日：2011-03-04

Applicant: Hee Seok EUN ,  Yong June KIM

Inventor： Hee Seok EUN ,  Yong June KIM

IPC: G11C16/10

CPC classification number: G11C16/10

Abstract: A nonvolatile memory device using interleaving technology is provided. The nonvolatile memory device includes a first controller configured to allocate one of 2N threshold voltage states to N-bit data where N is 2 or a natural number greater than 2, a second controller configured to set a difference between adjacent threshold voltage states among the 2N threshold voltage states so that the difference increases as a threshold voltage increases, and a programming unit configured to form a threshold voltage distribution state corresponding to the allocated threshold voltage state and to program the N-bit data to a multi-level cell. The second controller controls the difference between the adjacent threshold voltage states to equalize the number of read errors for all intersections among the 2N threshold voltage states at the end of life.

Abstract translation: 提供了一种使用交错技术的非易失性存储器件。 非易失性存储器件包括：第一控制器，被配置为将2N个阈值电压状态中的一个分配给N为2或大于2的自然数的N位数据;第二控制器，被配置为将2N的阈值电压状态之间的差设定为2N 阈值电压状态使得差异随阈值电压增加而增加，并且编程单元被配置为形成与所分配的阈值电压状态相对应的阈值电压分布状态，并将N位数据编程到多电平单元。 第二控制器控制相邻阈值电压状态之间的差异，以平衡在寿命结束时的2N个阈值电压状态之间的所有交点的读取误差的数量。

公开(公告)号：US20100248634A1

公开(公告)日：2010-09-30

申请号：US12741952

申请日：2008-06-30

Applicant: Taegyun Noh ,  Byung Jang Jeong ,  Hyun Kyu Chung ,  Dae Woon Lim ,  Min Joong Lim ,  Ho Yun Kim ,  Yong June Kim

Inventor： Taegyun Noh ,  Byung Jang Jeong ,  Hyun Kyu Chung ,  Dae Woon Lim ,  Min Joong Lim ,  Ho Yun Kim ,  Yong June Kim

IPC: H04B15/00

CPC classification number: H04L1/206

Abstract: Disclosed are an apparatus and method of determining an optimal cyclic delay value. The method of determining the optimal cyclic delay value includes determining a Signal-to-Interference and Noise Ratio (SINR) function depending on a diversity order; determining a channel estimation error variance function; and determining an SINR being required for a system according to the SINR function and the channel estimation error variance function.

Abstract translation: 公开了一种确定最佳循环延迟值的装置和方法。 确定最佳循环延迟值的方法包括根据分集顺序确定信号与干扰和噪声比（SINR）函数; 确定信道估计误差方差函数; 以及根据SINR功能和信道估计误差方差函数确定系统所需的SINR。

公开(公告)号：US20100246286A1

公开(公告)日：2010-09-30

申请号：US12656762

申请日：2010-02-16

Applicant: Yong June Kim ,  Jaehong Kim ,  Heeseok Eun

Inventor： Yong June Kim ,  Jaehong Kim ,  Heeseok Eun

IPC: G11C7/00

CPC classification number: G11C7/1006 ,  G06F11/1048 ,  G11C16/3404 ,  G11C2029/0411

Abstract: In a method of operating a nonvolatile memory device, data is read using a read level, and a range of logic values for erasure-decoding the read data is set. The bits of the read data corresponding to the set range of logic values are set as erasure bits, and an erasure decoding operation is performed.

Abstract translation: 在非易失性存储器件的操作方法中，使用读取级别读取数据，并且设置用于对读取数据进行擦除解码的逻辑值的范围。 对应于设定的逻辑值范围的读取数据的位被设置为擦除位，并且执行擦除解码操作。