公开(公告)号：US08345487B2

公开(公告)日：2013-01-01

申请号：US12774814

申请日：2010-05-06

申请人： Yong June Kim ,  Jae Hong Kim ,  Jun Jin Kong ,  Hong Rak Son ,  Seung-Hwan Song

发明人： Yong June Kim ,  Jae Hong Kim ,  Jun Jin Kong ,  Hong Rak Son ,  Seung-Hwan Song

IPC分类号： G11C11/413

CPC分类号： G11C11/5642 ,  G11C29/00 ,  G11C2211/5634

摘要： A method setting a read voltage to minimize data read errors in a semiconductor memory device including multi-bit memory cells. In the method, a read voltage associated with a minimal number of read data error is set based on a statistic value of a voltage distribution corresponding to each one of a plurality of voltage states.

摘要翻译： 一种设置读取电压以最小化包括多位存储器单元的半导体存储器件中的数据读取错误的方法。 在该方法中，基于与多个电压状态中的每一个相对应的电压分布的统计值来设置与最小数量的读取数据错误相关联的读取电压。

公开(公告)号：US08274840B2

公开(公告)日：2012-09-25

申请号：US12498508

申请日：2009-07-07

申请人： Yong-June Kim ,  Jae-Hong Kim ,  Kyoung-Lae Cho ,  Seung-Hwan Song ,  Jun-Jin Kong

发明人： Yong-June Kim ,  Jae-Hong Kim ,  Kyoung-Lae Cho ,  Seung-Hwan Song ,  Jun-Jin Kong

IPC分类号： G11C11/34

CPC分类号： G11C16/16

摘要： Nonvolatile memory devices include support memory cell recovery during operations to erase blocks of nonvolatile (e.g., flash) memory cells. A nonvolatile memory system includes a flash memory device and a memory controller electrically coupled to the flash memory device. The memory controller is configured to control memory cell recovery operations within the flash memory device by issuing a first instruction(s) to the flash memory device that causes erased memory cells in the block of memory to become at least partially programmed memory cells and then issuing a second instruction(s) to the flash memory device that causes the at least partially programmed memory cells become fully erased.

摘要翻译： 非易失性存储器件包括在擦除非易失性（例如闪存）存储器单元块的操作期间的支持存储器单元恢复。 非易失性存储器系统包括闪存器件和电耦合到闪速存储器件的存储器控​​制器。 存储器控制器被配置为通过向闪存器件发出第一指令来控制闪存器件内的存储器单元恢复操作，该第一指令使存储器块中的擦除存储器单元变成至少部分被编程的存储器单元，然后发出 使闪存器件的至少部分编程的存储器单元完全被擦除的第二指令。

公开(公告)号：US20100091578A1

公开(公告)日：2010-04-15

申请号：US12498508

申请日：2009-07-07

申请人： Yong-June Kim ,  Jae-Hong Kim ,  Kyoung-Lae Cho ,  Seung-Hwan Song ,  Jun-Jin Kong

发明人： Yong-June Kim ,  Jae-Hong Kim ,  Kyoung-Lae Cho ,  Seung-Hwan Song ,  Jun-Jin Kong

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/16

摘要： Nonvolatile memory devices include support memory cell recovery during operations to erase blocks of nonvolatile (e.g., flash) memory cells. A nonvolatile memory system includes a flash memory device and a memory controller electrically coupled to the flash memory device. The memory controller is configured to control memory cell recovery operations within the flash memory device by issuing a first instruction(s) to the flash memory device that causes erased memory cells in the block of memory to become at least partially programmed memory cells and then issuing a second instruction(s) to the flash memory device that causes the at least partially programmed memory cells become fully erased.

摘要翻译： 非易失性存储器件包括在擦除非易失性（例如闪存）存储器单元块的操作期间的支持存储器单元恢复。 非易失性存储器系统包括闪存器件和电耦合到闪速存储器件的存储器控​​制器。 存储器控制器被配置为通过向闪存器件发出第一指令来控制闪存器件内的存储器单元恢复操作，该第一指令使存储器块中的擦除存储器单元变成至少部分被编程的存储器单元，然后发出 使闪存器件的至少部分编程的存储器单元完全被擦除的第二指令。

公开(公告)号：US08200607B2

公开(公告)日：2012-06-12

申请号：US12292539

申请日：2008-11-20

申请人： Jae Hong Kim ,  Heeseok Eun ,  Yong June Kim ,  Jun Jin Kong ,  Seung-Hwan Song

发明人： Jae Hong Kim ,  Heeseok Eun ,  Yong June Kim ,  Jun Jin Kong ,  Seung-Hwan Song

IPC分类号： G06F17/00 ,  G06N5/02

CPC分类号： G06N99/005

摘要： Disclosed are a memory device and a data decision method. The memory device may include a memory cell array, and a decision unit configured to read first data from the memory cell array via a first channel, perform at least one of a hard and soft decision on the first data using a first number of decision levels set based on characteristics of the first channel, read second data from the memory cell array via a second channel, and perform a soft decision on the second data using a second number of decision levels set based on characteristics of the second channel.

摘要翻译： 公开了一种存储器件和数据判定方法。 存储器装置可以包括存储单元阵列，以及判定单元，被配置为经由第一通道从存储单元阵列读取第一数据，使用第一数量的判定级别对第一数据执行硬判决和软判决中的至少一个 基于第一信道的特性设置，经由第二信道从存储器单元阵列读取第二数据，并且使用基于第二信道的特性设置的第二数量的判定级来对第二数据执行软判决。

公开(公告)号：US20090234792A1

公开(公告)日：2009-09-17

申请号：US12292539

申请日：2008-11-20

申请人： Jae Hong Kim ,  Heeseok Eun ,  Yong June Kim ,  Jun Jin Kong ,  Seung-Hwan Song

发明人： Jae Hong Kim ,  Heeseok Eun ,  Yong June Kim ,  Jun Jin Kong ,  Seung-Hwan Song

IPC分类号： G06N5/00

CPC分类号： G06N99/005

摘要： Disclosed are a memory device and a data decision method. The memory device may include a memory cell array, and a decision unit configured to read first data from the memory cell array via a first channel, perform at least one of a hard and soft decision on the first data using a first number of decision levels set based on characteristics of the first channel, read second data from the memory cell array via a second channel, and perform a soft decision on the second data using a second number of decision levels set based on characteristics of the second channel.

摘要翻译： 公开了一种存储器件和数据判定方法。 存储器装置可以包括存储单元阵列，以及判定单元，被配置为经由第一通道从存储单元阵列读取第一数据，使用第一数量的判定级别对第一数据执行硬判决和软判决中的至少一个 基于第一信道的特性设置，经由第二信道从存储器单元阵列读取第二数据，并且使用基于第二信道的特性设置的第二数量的判定级来对第二数据执行软判决。

公开(公告)号：US20080288853A1

公开(公告)日：2008-11-20

申请号：US11889410

申请日：2007-08-13

申请人： Jun Jin Kong ,  Jong Han Kim ,  Hong Rak Son ,  Young Hwan Lee ,  Sung Chung Park ,  Seung-Hwan Song

发明人： Jun Jin Kong ,  Jong Han Kim ,  Hong Rak Son ,  Young Hwan Lee ,  Sung Chung Park ,  Seung-Hwan Song

IPC分类号： H03M13/03

CPC分类号： H03M13/6362

摘要： A code puncturing apparatus and method is provided. The apparatus includes: a codeword selection unit selecting continuous n−1-number of mother codewords from mother codewords generated from k-bit effective information, where k denotes a natural number, and one redundancy bit; and a puncturing unit selecting k-number of redundancy bits from redundancy bits included in the n−1-number of mother codewords, deleting remaining redundancy bits, and rearranging the n−1-number of mother codewords into an n·k bit-target codeword. Accordingly, a code rate of an Error Control Code (ECC) can be raised.

摘要翻译： 提供了一种代码穿刺装置和方法。 该装置包括：码字选择单元，从k比特有效信息生成的母码中选择连续n-1个母码字，其中k表示自然数，一个冗余比特; 以及删截单元，从包含在n-1个母码字中的冗余比特中选择k个冗余比特，删除剩余的冗余比特，并将n-1个母码字重排为nk比特目标码字。 因此，可以提高错误控制码（ECC）的码率。

公开(公告)号：US07864574B2

公开(公告)日：2011-01-04

申请号：US12453108

申请日：2009-04-29

申请人： Kyoung Lae Cho ,  Yong June Kim ,  Seung-Hwan Song ,  Jun Jin Kong

发明人： Kyoung Lae Cho ,  Yong June Kim ,  Seung-Hwan Song ,  Jun Jin Kong

IPC分类号： G11C11/34

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C2211/5621

摘要： Provided are memory devices and memory programming methods. A memory device may include a multi-bit cell array including a plurality of multi-bit cells, a programming unit configured to program a first data page in the plurality of multi-bit cells and to program a second data page in the multi-bit cells with the programmed first data page, a first controller configured to divide the multi-bit cells with the programmed first data page into a first group and a second group, and a second controller configured to set a target threshold voltage interval of each of the multi-bit cells included in the first group based on first read voltage levels and the second data page, and to set a target threshold voltage interval of each of the multi-bit cells included in the second group based on second read threshold voltage levels and the second data page.

摘要翻译： 提供的是存储器件和存储器编程方法。 存储器件可以包括包括多个多位单元的多位单元阵列，编程单元，被配置为对多个多位单元中的第一数据页进行编程，并编程多位单元中的第二数据页 具有编程的第一数据页的单元，被配置为将多位单元与编程的第一数据页划分为第一组和第二组的第一控制器，以及配置成将每个的第一数据页的目标阈值电压间隔 基于第一读取电压电平和第二数据页面包括在第一组中的多位单元，并且基于第二读取阈值电压电平来设置包括在第二组中的每个多位单元的目标阈值电压间隔，以及 第二个数据页面。

公开(公告)号：US08773922B2

公开(公告)日：2014-07-08

申请号：US12614545

申请日：2009-11-09

申请人： Seung-Hwan Song ,  Jaehong Kim ,  Kyoung Lae Cho ,  Yong June Kim ,  Jun Jin Kong ,  Jong Han Kim

发明人： Seung-Hwan Song ,  Jaehong Kim ,  Kyoung Lae Cho ,  Yong June Kim ,  Jun Jin Kong ,  Jong Han Kim

IPC分类号： G11C7/06

CPC分类号： G11C16/26 ,  G11C11/5642 ,  G11C29/00 ,  G11C2211/5634

摘要： A non-volatile semiconductor memory device and related method of determining a read voltage are disclosed. The non-volatile semiconductor memory device includes; a memory cell array including a plurality of memory cells, a read voltage determination unit configured to determine an optimal read voltage by comparing reference data obtained during a program operation with comparative data obtained during a subsequent read operation and changing a current read voltage to a new read voltage based on a result of the comparison, and a read voltage generation unit configured to generate the new read voltage in response to a read voltage control signal provided by the read voltage determination unit.

摘要翻译： 公开了一种非易失性半导体存储器件及确定读取电压的相关方法。 非易失性半导体存储器件包括： 包括多个存储单元的存储单元阵列，读电压确定单元，被配置为通过将在编程操作期间获得的参考数据与在随后的读取操作期间获得的比较数据进行比较来确定最佳读取电压，并将当前读取电压改变为新的 基于比较结果的读取电压和读取电压生成单元，被配置为响应于由读取电压确定单元提供的读取电压控制信号而产生新的读取电压。

公开(公告)号：US20090285023A1

公开(公告)日：2009-11-19

申请号：US12453108

申请日：2009-04-29

申请人： Kyoung Lae Cho ,  Yong June Kim ,  Seung-Hwan Song ,  Jun Jin Kong

发明人： Kyoung Lae Cho ,  Yong June Kim ,  Seung-Hwan Song ,  Jun Jin Kong

IPC分类号： G11C16/02 ,  G11C7/00 ,  G11C16/06

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C2211/5621

摘要： Provided are memory devices and memory programming methods. A memory device may include a multi-bit cell array including a plurality of multi-bit cells, a programming unit configured to program a first data page in the plurality of multi-bit cells and to program a second data page in the multi-bit cells with the programmed first data page, a first controller configured to divide the multi-bit cells with the programmed first data page into a first group and a second group, and a second controller configured to set a target threshold voltage interval of each of the multi-bit cells included in the first group based on first read voltage levels and the second data page, and to set a target threshold voltage interval of each of the multi-bit cells included in the second group based on second read threshold voltage levels and the second data page.

摘要翻译： 提供的是存储器件和存储器编程方法。 存储器件可以包括包括多个多位单元的多位单元阵列，编程单元，被配置为对多个多位单元中的第一数据页进行编程，并编程多位单元中的第二数据页 具有编程的第一数据页的单元，被配置为将多位单元与编程的第一数据页划分为第一组和第二组的第一控制器，以及配置成将每个的第一数据页的目标阈值电压间隔 基于第一读取电压电平和第二数据页面包括在第一组中的多位单元，并且基于第二读取阈值电压电平来设置包括在第二组中的每个多位单元的目标阈值电压间隔，以及 第二个数据页面。

公开(公告)号：US20090222701A1

公开(公告)日：2009-09-03

申请号：US12219103

申请日：2008-07-16

申请人： Seung-Hwan Song ,  Kyoung Lae Cho ,  Jun Jin Kong ,  Jae Hong Kim

发明人： Seung-Hwan Song ,  Kyoung Lae Cho ,  Jun Jin Kong ,  Jae Hong Kim

IPC分类号： G06F11/00 ,  G06F12/16

CPC分类号： G11C11/56 ,  G06F11/1012 ,  G11C29/00

摘要： Example embodiments relate to an apparatus which may determine a length of data to be stored in a memory cell, and may store the data in a memory based on the determined length. A memory data storage apparatus according to example embodiments may, include: a determination unit that may determine a number of bits of data and a number of bits of data detection information to be stored in a memory cell; a data receiving unit that may receive data corresponding to the determined number of bits; an error correction coding unit that may perform an error correction coding with respect to the received data and generate data detection information corresponding to the number of bits of the data detection information; and a data storage unit that may store the received data and generated data detection information in the memory cell.

摘要翻译： 示例性实施例涉及可以确定要存储在存储器单元中的数据的长度的装置，并且可以基于所确定的长度将数据存储在存储器中。 根据示例实施例的存储器数据存储装置可以包括：确定单元，其可以确定要存储在存储器单元中的数据的位数和数据检测信息的位数; 数据接收单元，其可以接收与所确定的位数相对应的数据; 纠错编码单元，其可以对所接收的数据执行纠错编码，并生成与数据检测信息的位数相对应的数据检测信息; 以及数据存储单元，其可以将所接收的数据和生成的数据检测信息存储在存储单元中。