公开(公告)号：US20240004444A1

公开(公告)日：2024-01-04

申请号：US17855054

申请日：2022-06-30

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Karthik Rao ,  Indrani Paul ,  Dana Glenn Lewis ,  Brett Danier Anil Ramautarsingh ,  Jeffrey Ka-Chun Lui ,  Prasanthy Loganaathan ,  Jun Huang ,  Ho Hin Lau ,  Zhidong Xu

IPC: G06F1/26

CPC classification number: G06F1/26

Abstract: Methods and systems are disclosed for managing performance states of a data fabric of a system on chip (SoC). Techniques disclosed include determining a performance state of the data fabric based on data fabric bandwidth utilizations of respective components of the SoC. A metric, characteristic of a workload centric to cores of the SoC, is derived from hardware counters, and, based on the metric, it is determined whether to alter the performance state.

公开(公告)号：US20230418664A1

公开(公告)日：2023-12-28

申请号：US17846593

申请日：2022-06-22

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Donny Yi ,  Indrani Paul ,  Ashwini Chandrashekhara Holla

IPC: G06F9/48 ,  G06F9/38 ,  G06F9/50 ,  G06F9/30

CPC classification number: G06F9/4881 ,  G06F9/3836 ,  G06F9/5038 ,  G06F9/5044 ,  G06F9/30079

Abstract: An apparatus and method for efficiently scheduling tasks in a dynamic manner to multiple cores that support a heterogeneous computing architecture. A computing system includes multiple cores with at least two cores being capable of executing instructions of a same instruction set architecture (ISA), and therefore, are architecturally compatible. In an implementation, each of the at least two cores is a general-purpose central processing unit (CPU) core capable of executing instructions of a same ISA. However, the throughput and the power consumption greatly differ between the at least two cores based on their hardware designs. An operating system scheduler assigns a thread to a first core, and the first core measures thread dynamic behavior of the thread over a time interval. Based on the thread dynamic behavior, the scheduler reassigns the thread to a second core different from the first core.

公开(公告)号：US20230350480A1

公开(公告)日：2023-11-02

申请号：US18213596

申请日：2023-06-23

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Indrani Paul ,  Sriram Sambamurthy ,  Larry David Hewitt ,  Kevin M. Lepak ,  Samuel D. Naffziger ,  Adam Neil Calder Clark ,  Aaron Joseph Grenat ,  Steven Frederick Liepe ,  Sandhya Shyamasundar ,  Wonje Choi ,  Dana Glenn Lewis ,  Leonardo de Paula Rosa Piga

IPC: G06F1/3225 ,  G06F1/3234

CPC classification number: G06F1/3225 ,  G06F1/3275 ,  G06F1/3203

Abstract: Platform power management includes boosting performance in a platform power boost mode or restricting performance to keep a power or temperature under a desired threshold in a platform power cap mode. Platform power management exploits the mutually exclusive nature of activities and the associated headroom created in a temperature and/or power budget of a server platform to boost performance of a particular component while also keeping temperature and/or power below a threshold or budget.

公开(公告)号：US11703937B2

公开(公告)日：2023-07-18

申请号：US17483698

申请日：2021-09-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Mihir Shaileshbhai Doctor ,  Alexander J. Branover ,  Benjamin Tsien ,  Indrani Paul ,  Christopher T. Weaver ,  Thomas J. Gibney ,  Stephen V. Kosonocky ,  John P. Petry

IPC: G06F1/32 ,  G06F1/3287 ,  G06F1/3296 ,  G06F1/3234

CPC classification number: G06F1/3287 ,  G06F1/3265 ,  G06F1/3278 ,  G06F1/3296

Abstract: Devices and methods for linear addressing are provided. A device is provided which comprises a plurality of components having assigned registers used to store data to execute a program and a power management controller, in communication with the components. The power management controller is configured to send one of a request to remove power to the components and a request to reduce power to the components when it is determined that the components are idle, execute a first process of one of removing power and reducing power to the components and entering a reduced power state when an acknowledgement of the request is received and execute a second process of restoring power to the components when one or more of the components are indicated to be active.

公开(公告)号：US20230090126A1

公开(公告)日：2023-03-23

申请号：US17483694

申请日：2021-09-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Benjamin Tsien ,  Alexander J. Branover ,  Christopher T. Weaver ,  Indrani Paul ,  Mihir Shaileshbhai Doctor ,  John P. Petry ,  Stephen V. Kosonocky ,  Thomas J. Gibney ,  Jose G. Cruz ,  Pravesh Gupta ,  Chintan S. Patel

IPC: G06F1/3234 ,  G06F11/14 ,  G06F3/06

Abstract: Devices and methods for transitioning between power states of a device are provided. A program is executed using data stored in configuration registers assigned to a component of a device. For a first reduced power state, data of a first portion of the configuration registers is saved to the memory using a first set of linear address space. For a second reduced power state, data of a second portion of the configuration registers is saved to the memory using a second set of linear address space and data of a third portion of the configuration registers is saved to the memory using a third set of linear address space.

公开(公告)号：US20230031388A1

公开(公告)日：2023-02-02

申请号：US17390429

申请日：2021-07-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Benjamin Tsien ,  Indrani Paul ,  Alexander J. Branover ,  Thomas J. Gibney ,  Mihir Shaileshbhai Doctor ,  John P. Petry ,  Stephen V. Kosonocky ,  Christopher T. Weaver

IPC: G06F1/3203

Abstract: Systems, methods, and devices for integrated circuit power management. A mode of a power management state is entered, from the power management state, in response to an entry condition of the mode. A device that is otherwise powered off in the power management state is powered on in the mode of the power management state. In some implementations, the device includes a communications path between a second device and a third device. In some implementations, the device is in a power domain that is powered off in the power management state. In some implementations, the power domain is powered off in the mode. In some implementations, the device is powered on in the mode via a power rail that is specific to the mode. In some implementations, the entry condition of the mode includes an amount of data stored for display in a display buffer falling below a threshold amount.

公开(公告)号：US20210349517A1

公开(公告)日：2021-11-11

申请号：US17381664

申请日：2021-07-21

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Indrani Paul ,  Sriram Sambamurthy ,  Larry David Hewitt ,  Kevin M. Lepak ,  Samuel D. Naffziger ,  Adam Neil Calder Clark ,  Aaron Joseph Grenat ,  Steven Frederick Liepe ,  Sandhya Shyamasundar ,  Wonje Choi ,  Dana Glenn Lewis ,  Leonardo de Paula Rosa Piga

IPC: G06F1/3225 ,  G06F1/3234

Abstract: Platform power management includes boosting performance in a platform power boost mode or restricting performance to keep a power or temperature under a desired threshold in a platform power cap mode. Platform power management exploits the mutually exclusive nature of activities and the associated headroom created in a temperature and/or power budget of a server platform to boost performance of a particular component while also keeping temperature and/or power below a threshold or budget.

公开(公告)号：US20200379544A1

公开(公告)日：2020-12-03

申请号：US16428312

申请日：2019-05-31

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Indrani Paul ,  Sriram Sambamurthy ,  Larry David Hewitt ,  Kevin M. Lepak ,  Samuel D. Naffziger ,  Adam Neil Calder Clark ,  Aaron Joseph Grenat ,  Steven Frederick Liepe ,  Sandhya Shyamasundar ,  Wonje Choi ,  Dana Glenn Lewis ,  Leonardo de Paula Rosa Piga

IPC: G06F1/3225 ,  G06F1/3234

Abstract: Platform power management includes boosting performance in a platform power boost mode or restricting performance to keep a power or temperature under a desired threshold in a platform power cap mode. Platform power management exploits the mutually exclusive nature of activities and the associated headroom created in a temperature and/or power budget of a server platform to boost performance of a particular component while also keeping temperature and/or power below a threshold or budget.

公开(公告)号：US10168762B2

公开(公告)日：2019-01-01

申请号：US14857574

申请日：2015-09-17

Applicant: Advanced Micro Devices, Inc.

Inventor： Can Hankendi ,  Manish Arora ,  Indrani Paul

IPC: G06F1/32

Abstract: A computing system includes a set of computing resources and a datastore to store information representing a corresponding idle power consumption metric and a corresponding peak power consumption metric for each computing resource of the set. The computing system further includes a controller coupled to the set of computing resources and the datastore. The controller is to configure the set of computing resources to meet a power budget constraint for the set based on the corresponding idle power consumption metric and the corresponding peak power consumption metric for each computing resource of the set.

公开(公告)号：US20180364782A1

公开(公告)日：2018-12-20

申请号：US16011476

申请日：2018-06-18

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Leonardo De Paula Rosa Piga ,  Samuel Naffziger ,  Ivan Matosevic ,  Indrani Paul

IPC: G06F1/32

Abstract: A power management algorithm framework proposes: 1) a Quality-of-Service (QoS) metric for throughput-based workloads; 2) heuristics to differentiate between throughput and latency sensitive workloads; and 3) an algorithm that combines the heuristic and QoS metric to determine target frequency for minimizing idle time and improving power efficiency without any performance degradation. A management algorithm framework enables optimizing power efficiency in server-class throughput-based workloads while still providing desired performance for latency sensitive workloads. The power savings are achieved by identifying workloads in which one or more cores can be run at a lower frequency (and consequently lower power) without a significant negative performance impact.