公开(公告)号：US11422863B2

公开(公告)日：2022-08-23

申请号：US16020810

申请日：2018-06-27

Applicant: Amazon Technologies, Inc.

Inventor： Sudipta Sengupta ,  Poorna Chand Srinivas Perumalla ,  Dominic Rajeev Divakaruni ,  Nafea Bshara ,  Leo Parker Dirac ,  Bratin Saha ,  Matthew James Wood ,  Andrea Olgiati ,  Swaminathan Sivasubramanian

IPC: G06F9/50 ,  G06N5/04 ,  G06F9/455 ,  G06F9/38 ,  G06N20/00

Abstract: Implementations detailed herein include description of a computer-implemented method. In an implementation, the method at least includes provisioning an application instance and portions of at least one accelerator attached to the application instance to execute a machine learning model of an application of the application instance; loading the machine learning model onto the portions of the at least one accelerator; receiving scoring data in the application; and utilizing each of the portions of the attached at least one accelerator to perform inference on the scoring data in parallel and only using one response from the portions of the accelerator.

公开(公告)号：US11416749B2

公开(公告)日：2022-08-16

申请号：US16216873

申请日：2018-12-11

Applicant: Amazon Technologies, Inc.

Inventor： Nafea Bshara ,  Thomas A. Volpe

IPC: G06N3/10 ,  G06F9/30 ,  G06F9/54 ,  G06N3/063 ,  G06F9/38

Abstract: An integrated circuit includes a processing engine configured to execute instructions that are synchronized using a set of events. The integrated circuit also includes a set of event registers and an age bit register. Each event in the set of events corresponds to a respective event register in the set of event registers. The age bit register includes a set of age bits, where each age bit in the age bit register corresponds to a respective event register in the set of event registers. Each age bit in the age bit register is configured to be set by an external circuit and to be cleared in response to a value change in a corresponding event register in the set of event registers. Executing the instructions by the processing engine changes a value of an event register in the set of event registers.

公开(公告)号：US20220253392A1

公开(公告)日：2022-08-11

申请号：US17660797

申请日：2022-04-26

Applicant: Amazon Technologies, Inc.

Inventor： Nafea Bshara ,  Adi Habusha ,  Guy Nakibly ,  Georgy Machulsky

IPC: G06F13/10 ,  G06F13/24 ,  G06F13/42 ,  G06F9/50

Abstract: Techniques for emulating a configuration space may include emulating a set of configuration registers for a set of functions corresponding to a type of peripheral device. The set of functions can include a physical function and a virtual function associated with the physical function. A configuration access request can be processed by retrieving an emulated configuration register from the emulated configuration space, and logging incoming configuration access requests in a configuration transaction log to track configuration accesses.

公开(公告)号：US11275503B2

公开(公告)日：2022-03-15

申请号：US16863700

申请日：2020-04-30

Applicant: Amazon Technologies, Inc.

Inventor： Mark Bradley Davis ,  Erez Izenberg ,  Robert Michael Johnson ,  Asif Khan ,  Islam Mohamed Hatem Abdulfattah Mohamed Atta ,  Nafea Bshara ,  Christopher Joseph Pettey

IPC: G06F3/06 ,  G06F12/08 ,  G06F15/78 ,  G06F21/51 ,  G06F13/28 ,  G11C7/10

Abstract: Methods and apparatus are disclosed for securely erasing partitions of reconfigurable logic devices such as FPGAs in a multi-tenant server environment. In one example, a method of securely erasing an FPGA includes identifying one partition of previously-programmed resources in the FPGA, erasing the identified partition by storing new values in memory or storage elements of the identified partition, and storing new values in memory or storage elements of additional external resources electrically connected to the integrated circuit and associated with the identified partition. Thus, other partitions and subsequent users of the identified partition are prevented from accessing the securely erased data. A configuration circuit, accessible by a host computer via DMA, can be programmed into the FPGA reconfigurable logic for performing the disclosed erasing operations.

公开(公告)号：US20220060454A1

公开(公告)日：2022-02-24

申请号：US17518259

申请日：2021-11-03

Applicant: Amazon Technologies, Inc.

Inventor： Islam Mohamed Hatem Abdulfattah Mohamed Atta ,  Christopher Joseph Pettey ,  Nafea Bshara ,  Asif Khan ,  Mark Bradley Davis ,  Prateek Tandon

IPC: H04L29/06 ,  H04L9/32 ,  G06F15/78 ,  G06F9/50

Abstract: The following description is directed to a logic repository service. In one example, a method of a logic repository service can include receiving a first request to generate configuration data for configurable hardware using a specification for application logic of the configurable hardware. The method can include generating the configuration data for the configurable hardware. The configuration data can include data for implementing the application logic. The method can include encrypting the configuration data to generate encrypted configuration data. The method can include signing the encrypted configuration data using a private key. The method can include transmitting the signed encrypted configuration data in response to the request.

公开(公告)号：US11249937B1

公开(公告)日：2022-02-15

申请号：US16226529

申请日：2018-12-19

Applicant: Amazon Technologies, Inc.

Inventor： Nafea Bshara ,  Alexander Matushevsky ,  Georgy Machulsky ,  Leah Shalev ,  Saar Gross

IPC: G06F15/173 ,  H04L29/08 ,  G06F12/02 ,  G06F13/42 ,  H04L29/06

Abstract: Provided are systems and methods for a storage adapter device for communicating with network storage. In some implementations, the storage adapter device comprises a host interface. In these implementations, the host interface may be configured to communicate with a host device using a local bus protocol. In some implementations, the storage adapter device also includes a network interface. In these implementations, the network interface may communicate with a network using a network protocol. In some implementations, the storage adapter device may be configured to communicate with a remote storage device. In some implementations, the storage adapter device may also be configured to translate a request from the host interface from the local bus protocol to the network protocol. The storage adapter device may further be configured to transmit the translated request to the remote storage device.

公开(公告)号：US11249647B2

公开(公告)日：2022-02-15

申请号：US16435372

申请日：2019-06-07

Applicant: Amazon Technologies, Inc.

Inventor： Raviprasad Venkatesha Murthy Mummidi ,  Matthew Shawn Wilson ,  Anthony Nicholas Liguori ,  Nafea Bshara ,  Saar Gross ,  Jaspal Kohli

IPC: G06F3/06 ,  G06F12/14 ,  G06F13/20 ,  G06F13/40

Abstract: A peripheral device may implement storage virtualization for non-volatile storage devices connected to the peripheral device. A host system connected to the peripheral device may host one or multiple virtual machines. The peripheral device may implement different virtual interfaces for the virtual machines or the host system that present a storage partition at a non-volatile storage device to the virtual machine or host system for storage. Access requests from the virtual machines or host system are directed to the respective virtual interface at the peripheral device. The peripheral device may perform data encryption or decryption, or may perform throttling of access requests. The peripheral device may generate and send physical access requests to perform the access requests received via the virtual interfaces to the non-volatile storage devices. Completion of the access requests may be indicated to the virtual machines via the virtual interfaces.

公开(公告)号：US11115293B2

公开(公告)日：2021-09-07

申请号：US15354765

申请日：2016-11-17

Applicant: Amazon Technologies, Inc.

Inventor： Robert Michael Johnson ,  Nafea Bshara ,  Matthew Shawn Wilson

IPC: H04L12/24 ,  G06F9/50 ,  G06F15/78

Abstract: Methods and apparatus are disclosed for programming reconfigurable logic devices such as FPGAs in a networked server environment. In one example, a system hosting a network service providing field programmable gate array (FPGA) services includes a network service provider configured to receive a request to implement application logic in a plurality of FPGAs, allocate a computing instance comprising the FPGAs in responses to receiving the request, produce configuration information for programming the FPGAs, and send the configuration information to an allocated computing instance. The system further includes a computing host that is allocated by the network service provider as a computing instance which includes memory, processors configured to execute computer-executable instructions stored in the memory, and the programmed FPGAs.

公开(公告)号：US11003618B1

公开(公告)日：2021-05-11

申请号：US15635038

申请日：2017-06-27

Applicant: Amazon Technologies, Inc.

Inventor： Kypros Constantinides ,  Nafea Bshara ,  Matthew Shawn Wilson

IPC: G06F13/40 ,  G06F13/42 ,  G06T1/20 ,  G06F9/455

Abstract: Disclosed are techniques regarding aspects of selectively enabling or disabling interconnects between peripheral processors. The peripheral processors may be included within a compute service provider and may be accessible via virtual machines within guest domains implemented within the compute service provider. The interconnects can be enabled or disabled depending upon whether they traverse domains of the compute service provider.

公开(公告)号：US10901492B1

公开(公告)日：2021-01-26

申请号：US16369696

申请日：2019-03-29

Applicant: Amazon Technologies, Inc.

Inventor： Nafea Bshara ,  Ron Diamant ,  Randy Renfu Huang ,  Ali Ghassan Saidi

IPC: G06F1/26 ,  G06F1/32 ,  G06F1/329 ,  G06F7/523 ,  G06F7/57 ,  G06F9/30

Abstract: Techniques are described for power reduction in a computer processor based on detection of whether data destined for input to an arithmetic logic unit (ALU) has a particular value. The data is written to a register prior to performing an arithmetic or logical operation using the data as an operand. Depending on a timing of when the data is supplied to the register, the determination is made before or after the data is written to the register, and a memory associated with the register is updated with a result of the determination. Contents of the memory are used to make a decision whether to allow the ALU to perform the arithmetic or logical operation. The memory can be implemented as a non-architectural register.