公开(公告)号：US08230119B2

公开(公告)日：2012-07-24

申请号：US12861439

申请日：2010-08-23

申请人： Jasmin Ajanovic ,  Mahesh Wagh ,  Prashant Sethi ,  Debendra Das Sharma ,  David Harriman ,  Mark Rosenbluth ,  Ajay Bhatt ,  Peter Barry ,  Scott Dion Rodgers ,  Anil Vasudevan ,  Sridhar Muthrasanallur ,  James Akiyama ,  Robert Blankenship ,  Ohad Falik ,  Abraham Mendelson ,  Ilan Pardo ,  Eran Tamari ,  Eliezer Weissmann ,  Doron Shamia

发明人： Jasmin Ajanovic ,  Mahesh Wagh ,  Prashant Sethi ,  Debendra Das Sharma ,  David Harriman ,  Mark Rosenbluth ,  Ajay Bhatt ,  Peter Barry ,  Scott Dion Rodgers ,  Anil Vasudevan ,  Sridhar Muthrasanallur ,  James Akiyama ,  Robert Blankenship ,  Ohad Falik ,  Abraham Mendelson ,  Ilan Pardo ,  Eran Tamari ,  Eliezer Weissmann ,  Doron Shamia

IPC分类号： G06F3/00 ,  G06F13/20

CPC分类号： G06F12/0831 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3253 ,  G06F12/0815 ,  G06F13/385 ,  G06F13/4045 ,  G06F13/4068 ,  G06F13/4265 ,  G06F2212/621 ,  H04L12/66 ,  Y02D10/126 ,  Y02D10/151

摘要： A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

摘要翻译： 这里描述了用于增强/扩展串行点对点互连架构的方法和装置，例如外围组件互连Express（PCIe）。 提供了时间和地点缓存提示和预取提示，以改进系统范围的缓存和预取。 包括用于仲裁系统设备/资源之间的所有权的原子操作的消息代码，以便有效地访问/拥有共享数据。 提供的松散的事务排序，同时将对应的事务优先级保持到内存位置，以确保数据完整性和高效的内存访问。 包括有功功率子状态及其设置以允许更有效的电源管理。 并且，提供设备本地存储器在主机地址空间中的缓存以及设备本地存储器地址空间中的系统存储器的缓存，以提高存储器访问的带宽和延迟。

公开(公告)号：US20120089750A1

公开(公告)日：2012-04-12

申请号：US13316349

申请日：2011-12-09

申请人： Jasmin Ajanovic ,  Mahesh Wagh ,  Prashant Sethi ,  Debendra Das Sharma ,  David Harriman ,  Mark Rosenbluth ,  Ajay Bhatt ,  Peter Barry ,  Scott Dion Rodgers ,  Anil Vasudevan ,  Sridhar Muthrasanallur ,  James Akiyama ,  Robert Blankenship ,  Ohad Falik ,  Avi (Abraham) Mendelson ,  Ilan Pardo ,  Eran Tamari ,  Eliezer Weissmann ,  Doron Shamia

发明人： Jasmin Ajanovic ,  Mahesh Wagh ,  Prashant Sethi ,  Debendra Das Sharma ,  David Harriman ,  Mark Rosenbluth ,  Ajay Bhatt ,  Peter Barry ,  Scott Dion Rodgers ,  Anil Vasudevan ,  Sridhar Muthrasanallur ,  James Akiyama ,  Robert Blankenship ,  Ohad Falik ,  Avi (Abraham) Mendelson ,  Ilan Pardo ,  Eran Tamari ,  Eliezer Weissmann ,  Doron Shamia

IPC分类号： G06F3/00

CPC分类号： G06F12/0831 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3253 ,  G06F12/0815 ,  G06F13/385 ,  G06F13/4045 ,  G06F13/4068 ,  G06F13/4265 ,  G06F2212/621 ,  H04L12/66 ,  Y02D10/126 ,  Y02D10/151

摘要： A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

摘要翻译： 这里描述了用于增强/扩展串行点对点互连架构的方法和装置，例如外围组件互连Express（PCIe）。 提供了时间和地点缓存提示和预取提示，以改进系统范围的缓存和预取。 包括用于仲裁系统设备/资源之间的所有权的原子操作的消息代码，以便有效地访问/拥有共享数据。 提供的松散的事务排序，同时将对应的事务优先级保持到内存位置，以确保数据完整性和高效的内存访问。 包括有功功率子状态及其设置以允许更有效的电源管理。 并且，提供设备本地存储器在主机地址空间中的缓存以及设备本地存储器地址空间中的系统存储器的缓存，以提高存储器访问的带宽和延迟。

公开(公告)号：US20110161703A1

公开(公告)日：2011-06-30

申请号：US13046345

申请日：2011-03-11

申请人： Jasmin Ajanovic ,  Mahesh Wagh ,  Prashant Sethi ,  Debendra Das Sharma ,  David Harriman ,  Mark Rosenbluth ,  Ajay Bhatt ,  Peter Barry ,  Scott Dion Rodgers ,  Anil Vasudevan ,  Sridhar Muthrasanallur ,  James Akiyama ,  Robert Blankenship ,  Ohad Falik ,  Avi Abraham Mendelson ,  Ilan Pardo ,  Eran Tamari ,  Eliezer Weissmann ,  Doron Shamia

发明人： Jasmin Ajanovic ,  Mahesh Wagh ,  Prashant Sethi ,  Debendra Das Sharma ,  David Harriman ,  Mark Rosenbluth ,  Ajay Bhatt ,  Peter Barry ,  Scott Dion Rodgers ,  Anil Vasudevan ,  Sridhar Muthrasanallur ,  James Akiyama ,  Robert Blankenship ,  Ohad Falik ,  Avi Abraham Mendelson ,  Ilan Pardo ,  Eran Tamari ,  Eliezer Weissmann ,  Doron Shamia

IPC分类号： G06F1/32

CPC分类号： G06F12/0831 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3253 ,  G06F12/0815 ,  G06F13/385 ,  G06F13/4045 ,  G06F13/4068 ,  G06F13/4265 ,  G06F2212/621 ,  H04L12/66 ,  Y02D10/126 ,  Y02D10/151

摘要： A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

公开(公告)号：US07809969B2

公开(公告)日：2010-10-05

申请号：US11321116

申请日：2005-12-28

申请人： Debendra Das Sharma ,  Ajay V. Bhatt

发明人： Debendra Das Sharma ,  Ajay V. Bhatt

IPC分类号： G06F1/32

CPC分类号： G06F1/3203 ,  G06F1/3253 ,  Y02D10/151

摘要： A method, device, and system are disclosed. In one embodiment, the method comprises transitioning one or more lanes of a multi-lane serial link from a fully operational power state to a low power state and keeping one or more other lanes of the multi-lane serial link in the fully operational power state to allow one or more data transfers across the remaining operational lanes in the link.

摘要翻译： 公开了一种方法，装置和系统。 在一个实施例中，该方法包括将多通道串行链路的一个或多个通道从完全操作的功率状态转换到低功率状态，并将多通道串行链路的一个或多个其他通道保持在完全操作的功率状态 允许在链路中的剩余操作通道上进行一个或多个数据传输。

公开(公告)号：US20100199120A1

公开(公告)日：2010-08-05

申请号：US12756998

申请日：2010-04-08

申请人： Debendra Das Sharma ,  Gurushankar Rajamani ,  Hanh Hoang

发明人： Debendra Das Sharma ,  Gurushankar Rajamani ,  Hanh Hoang

IPC分类号： G06F1/04

CPC分类号： H04L49/9078 ,  H04L49/90

摘要： Various embodiments of the invention provide a frequency shifter to vary the frequency of data transmitted over time, such as to increase and decrease the frequency of test data transmitted over time to verify a digital communication device's ability to receive data having various frequencies within a specific parameter range. The frequency shifter includes a frequency modifier to shift or vary an input clock frequency to a variety of output clock frequencies, such as according to a test protocol. The frequency shifter also includes an elastic data buffer to receive the test data at the input clock frequency and to output the test data at the plurality of output clock frequencies provided by the frequency modifier.

摘要翻译： 本发明的各种实施例提供一种频率移位器来改变随时间传输的数据的频率，诸如增加和减少随时间传输的测试数据的频率，以验证数字通信设备接收具有特定参数内的各种频率的数据的能力 范围。 频移器包括频率修正器，用于将输入时钟频率移位或改变为各种输出时钟频率，例如根据测试协议。 移相器还包括一个弹性数据缓冲器，用于以输入时钟频率接收测试数据，并输出由频率调节器提供的多个输出时钟频率的测试数据。

公开(公告)号：US07730376B2

公开(公告)日：2010-06-01

申请号：US12056777

申请日：2008-03-27

申请人： Debendra Das Sharma

发明人： Debendra Das Sharma

IPC分类号： G01R31/28 ,  G06F11/00

CPC分类号： G06F11/0751 ,  G06F11/0745

摘要： A method, device, and system are disclosed. In one embodiment, the method comprises discovering a failure on a PCI Express interconnect, determining whether a failure override bit has been set to override the standard PCI Express Polling. Compliance state for the failure on the PCI Express interconnect, and if the failure override bit has been set, entering PCI Express Polling. Configuration state if any one lane of the interconnect successfully completes the transmitting and receiving training sequence requirements in PCI Express Polling.Active state.

摘要翻译： 公开了一种方法，装置和系统。 在一个实施例中，该方法包括发现PCI Express互连上的故障，确定故障覆盖位是否被设置为覆盖标准PCI Express轮询。 PCI Express互连失败的合规状态，如果故障覆盖位已经设置，进入PCI Express轮询。 配置状态如果互连的任何一个通道成功完成了PCI Express Polling.Active状态下的发送和接收训练序列要求。

公开(公告)号：US07505486B2

公开(公告)日：2009-03-17

申请号：US10300444

申请日：2002-11-19

申请人： Debendra Das Sharma

发明人： Debendra Das Sharma

IPC分类号： H04J3/04 ,  G01R31/08

CPC分类号： H04L1/0002 ,  H04J3/14 ,  Y02D50/10

摘要： A method an apparatus of communicating data, such as in a sending node or a receiving node of networked system, includes transmitting via a network connection having at least M data channels at least one data block, the data block having M data bits having an original data bit order, in a full transmission bit order at a full data block transmission rate via a full network data path comprising M functioning data channels. The method and apparatus further includes transmitting the at least one data block in a degraded transmission bit order at a degraded data block transmission rate via a selected degraded network data path comprising at least one, but less than M, functioning data channels.

摘要翻译： 一种传送数据的装置，例如在联网系统的发送节点或接收节点中的方法，包括通过具有至少一个数据块的至少M个数据信道的网络连接发送，具有M个数据位的数据块具有原始 数据位顺序，通过包括M个功能数据信道的完整网络数据路径以完全数据块传输速率的全传输位顺序。 所述方法和装置还包括以降级的数据块传输速率通过包括至少一个但小于M个功能的数据信道的选定的退化网络数据路径，以恶化的传输比特顺序发送所述至少一个数据块。

公开(公告)号：US07464287B2

公开(公告)日：2008-12-09

申请号：US10815903

申请日：2004-03-31

申请人： Debendra Das Sharma ,  Gurushankar Rajamani ,  Hanh Hoang

发明人： Debendra Das Sharma ,  Gurushankar Rajamani ,  Hanh Hoang

IPC分类号： G06F5/06 ,  G06F17/50 ,  G06F7/62

CPC分类号： H04L49/9078 ,  H04L49/90

摘要： Various embodiments of the invention provide a frequency shifter to vary the frequency of data transmitted over time, such as to increase and decrease the frequency of test data transmitted over time to verify a digital communication device's ability to receive data having various frequencies within a specific parameter range. The frequency shifter includes a frequency modifier to shift or vary an input clock frequency to a variety of output clock frequencies, such as according to a test protocol. The frequency shifter also includes an elastic data buffer to receive the test data at the input clock frequency and to output the test data at the plurality of output clock frequencies provided by the frequency modifier.

摘要翻译： 本发明的各种实施例提供一种频率移位器来改变随时间传输的数据的频率，诸如增加和减少随时间传输的测试数据的频率，以验证数字通信设备接收具有特定参数内的各种频率的数据的能力 范围。 频移器包括频率修正器，用于将输入时钟频率移位或改变为各种输出时钟频率，例如根据测试协议。 移相器还包括一个弹性数据缓冲器，用于以输入时钟频率接收测试数据，并输出由频率调节器提供的多个输出时钟频率的测试数据。

公开(公告)号：US20080195780A1

公开(公告)日：2008-08-14

申请号：US11933126

申请日：2007-10-31

申请人： Jasmin Ajanovic ,  Mahesh Wagh ,  Prashant Sethi ,  Debendra Das Sharma ,  David Harriman ,  Mark Rosenbluth ,  Ajay Bhatt ,  Peter Barry ,  Scott Dion Rodgers ,  Anil Vasudevan ,  Sridhar Muthrasanallur ,  James Akiyama ,  Robert Blankenship ,  Ohad Falik ,  Avi (Arraham) Mendelson ,  Ilan Pardo ,  Eran Tamari ,  Eliezer Weissmann ,  Doron Shamia

发明人： Jasmin Ajanovic ,  Mahesh Wagh ,  Prashant Sethi ,  Debendra Das Sharma ,  David Harriman ,  Mark Rosenbluth ,  Ajay Bhatt ,  Peter Barry ,  Scott Dion Rodgers ,  Anil Vasudevan ,  Sridhar Muthrasanallur ,  James Akiyama ,  Robert Blankenship ,  Ohad Falik ,  Avi (Arraham) Mendelson ,  Ilan Pardo ,  Eran Tamari ,  Eliezer Weissmann ,  Doron Shamia

IPC分类号： G06F13/42

CPC分类号： G06F12/0831 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3253 ,  G06F12/0815 ,  G06F13/385 ,  G06F13/4045 ,  G06F13/4068 ,  G06F13/4265 ,  G06F2212/621 ,  H04L12/66 ,  Y02D10/126 ,  Y02D10/151

摘要： A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

公开(公告)号：US20080040566A1

公开(公告)日：2008-02-14

申请号：US11973209

申请日：2007-10-05

申请人： Robert Safranek ,  Debendra Das Sharma

发明人： Robert Safranek ,  Debendra Das Sharma

IPC分类号： G06F12/14

CPC分类号： G06F12/1425 ,  G06F12/1441 ,  G06F12/145

摘要： A NoDMA cache including a super page field. The super page field indicates when a set of pages contain protected information. The NoDMA cache is used by a computer system to deny I/O device access to protected information in system memory.

摘要翻译： 包含超级页面字段的NoDMA缓存。 超级页面字段指示一组页面何时包含受保护的信息。 计算机系统使用NoDMA缓存来拒绝I / O设备访问系统内存中受保护的信息。