公开(公告)号：US10805392B2

公开(公告)日：2020-10-13

申请号：US15221554

申请日：2016-07-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Amin Farmahini-Farahani ,  David A. Roberts

IPC: G06F15/16 ,  H04L29/08

Abstract: Devices, methods, and systems for distributed gather and scatter operations in a network of memory nodes. A responding memory node includes a memory; a communications interface having circuitry configured to communicate with at least one other memory node; and a controller. The controller includes circuitry configured to receive a request message from a requesting node via the communications interface. The request message indicates a gather or scatter operation, and instructs the responding node to retrieve data elements from a source memory data structure and store the data elements to a destination memory data structure. The controller further includes circuitry configured to transmit a response message to the requesting node via the communications interface. The response message indicates that the data elements have been stored into the destination memory data structure.

公开(公告)号：US10592279B2

公开(公告)日：2020-03-17

申请号：US15191355

申请日：2016-06-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Arkaprava Basu ,  Dmitri Yudanov ,  David A. Roberts ,  Mitesh R. Meswani ,  Sergey Blagodurov

IPC: G06F9/52 ,  G06F9/48 ,  G06F11/34 ,  G06F9/50

Abstract: A method and processing apparatus for accelerating program processing is provided that includes a plurality of processors configured to process a plurality of tasks of a program and a controller. The controller is configured to determine, from the plurality of tasks being processed by the plurality of processors, a task being processed on a first processor to be a lagging task causing a delay in execution of one or more other tasks of the plurality of tasks. The controller is further configured to provide the determined lagging task to a second processor to be executed by the second processor to accelerate execution of the lagging task.

公开(公告)号：US20190252385A1

公开(公告)日：2019-08-15

申请号：US15895799

申请日：2018-02-13

Applicant: Advanced Micro Devices, Inc.

Inventor： Dmitri Yudanov ,  David A. Roberts

IPC: H01L27/108 ,  G11C11/406 ,  G11C11/408

CPC classification number: H01L27/10805 ,  G11C11/40611 ,  G11C11/4085

Abstract: A modified 1C1T cell detects when the charge in the memory cell drops below a predetermined voltage due to leakage and asserts a refresh signal indicating that refresh needs to be performed on those memory cells associated with the modified 1C1T memory cell. The associated memory cells may be a row, a bank, or other groupings of memory cells. Because temperature affects leakage current, the modified memory cell automatically adjusts for temperature.

公开(公告)号：US20190205253A1

公开(公告)日：2019-07-04

申请号：US15857837

申请日：2017-12-29

Applicant: Advanced Micro Devices, Inc.

Inventor： David A. Roberts

IPC: G06F12/0846 ,  G06F12/0862 ,  G06F12/0815

CPC classification number: G06F12/0848 ,  G06F12/0815 ,  G06F12/0862 ,  G06F2212/282 ,  G06F2212/602 ,  G06F2212/621

Abstract: A method and apparatus physically partitions clean and dirty cache lines into separate memory partitions, such as one or more banks, so that during low power operation, a cache memory controller reduces power consumption of the cache memory containing the clean only data. The cache memory controller controls a refresh operation so that a data refresh does not occur for the clean data only banks or the refresh rate is reduced for the clean data only banks. Partitions that store dirty data can also store clean data; however, other partitions are designated for storing only clean data so that the partitions can have their refresh rate reduced or refresh stopped for periods of time. When multiple DRAM dies or packages are employed, the partition can occur on a die or package level as opposed to a bank level within a die.

公开(公告)号：US10310997B2

公开(公告)日：2019-06-04

申请号：US15273013

申请日：2016-09-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Amin Farmahini Farahani ,  David A. Roberts ,  Nuwan Jayasena

IPC: G06F12/0802 ,  G06F13/16

Abstract: A processing system employs a memory module as a temporary write buffer to store write requests when a write buffer at a memory controller reaches a threshold capacity, and de-allocates the temporary write buffer when the write buffer capacity falls below the threshold. Upon receiving a write request, the memory controller stores the write request in a write buffer until the write request can be written to main memory. The memory controller can temporarily extend the memory controller's write buffer to the memory module, thereby accommodating temporary periods of high memory activity without requiring a large permanent write buffer at the memory controller.

公开(公告)号：US20190146829A1

公开(公告)日：2019-05-16

申请号：US15809940

申请日：2017-11-10

Applicant: Advanced Micro Devices, Inc.

Inventor： Kevin Y. Cheng ,  David A. Roberts ,  William C. Brantley

IPC: G06F9/46 ,  G06F9/50 ,  G06F13/40 ,  G06F13/42

Abstract: A hardware context manager in a field-programmable gate array (FPGA) device includes configuration logic configured to program one or more programming regions in the FPGA device based on configuration data for implementing a target configuration of the one or more programming regions. Context management logic in the hardware context manager is coupled with the configuration logic and saves a first context corresponding to the target configuration by retrieving first state information from the set of one or more programming regions, where the first state information is generated based on the target configuration, and storing the retrieved first state information in a context memory. The context management logic restores the first context by transferring the first state information from the context memory to the one or more programming regions, and causing the configuration logic to program the one or more programming regions based on the configuration data.

公开(公告)号：US10209991B2

公开(公告)日：2019-02-19

申请号：US15353161

申请日：2016-11-16

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Meenakshi Sundaram Bhaskaran ,  Elliot H. Mednick ,  David A. Roberts ,  Anthony Asaro ,  Amin Farmahini-Farahani

IPC: G06F9/30 ,  G06F9/38 ,  G06F12/084 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/1027

Abstract: A system and method for reducing latencies of main memory data accesses are described. A non-blocking load (NBLD) instruction identifies an address of requested data and a subroutine. The subroutine includes instructions dependent on the requested data. A processing unit verifies that address translations are available for both the address and the subroutine. The processing unit continues processing instructions with no stalls caused by younger-in-program-order instructions waiting for the requested data. The non-blocking load unit performs a cache coherent data read request on behalf of the NBLD instruction and requests that the processing unit perform an asynchronous jump to the subroutine upon return of the requested data from lower-level memory.

公开(公告)号：US20190051576A1

公开(公告)日：2019-02-14

申请号：US15674607

申请日：2017-08-11

Applicant: Advanced Micro Devices, Inc.

Inventor： David A. Roberts ,  Greg Sadowski ,  Steven Raasch

IPC: H01L23/34 ,  H01L25/065 ,  G05B15/02

Abstract: Exemplary embodiments provide thermal wear spreading among a plurality of thermal die regions in an integrated circuit or among dies by using die region wear-out data that represents a cumulative amount of time each of a number of thermal die regions in one or more dies has spent at a particular temperature level. In one example, die region wear-out data is stored in persistent memory and is accrued over a life of each respective thermal region so that a long term monitoring of temperature levels in the various die regions is used to spread thermal wear among the thermal die regions. In one example, spreading thermal wear is done by controlling task execution such as thread execution among one or more processing cores, dies and/or data access operations for a memory.

公开(公告)号：US20190034251A1

公开(公告)日：2019-01-31

申请号：US15662524

申请日：2017-07-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Vilas Sridharan ,  David A. Roberts

IPC: G06F11/00 ,  G06F11/30 ,  G06F11/34

Abstract: Described herein are a method and apparatus for memory vulnerability prediction. A memory vulnerability predictor predicts the reliability of a memory region when it is first accessed, based on past program history. The memory vulnerability predictor uses a table to store reliability predictions and predicts reliability needs of a new memory region. A memory management module uses the reliability information to make decisions, (such as to guide memory placement policies in a heterogeneous memory system).

公开(公告)号：US20180337863A1

公开(公告)日：2018-11-22

申请号：US15600048

申请日：2017-05-19

Applicant: Advanced Micro Devices, Inc.

Inventor： David A. Roberts

IPC: H04L12/833 ,  H04L12/707 ,  H04L12/46

Abstract: The described embodiments include an electronic device that handles network packets. During operation, the electronic device receives a carrier packet, the carrier packet that includes a tunneled packet in a payload of the carrier packet, wherein the tunneled packet includes a packet priority of the tunneled packet and the carrier packet includes a packet priority of the carrier packet. The electronic device then updates the packet priority of the carrier packet based on the packet priority of the tunneled packet.