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    USE OF CONTACTS TO CREATE DIFFERENTIAL STRESSES ON DEVICES
    91.
    发明申请
    USE OF CONTACTS TO CREATE DIFFERENTIAL STRESSES ON DEVICES 有权
    使用联系人创建设备上的差别应力

    公开(公告)号：US20120074501A1

    公开(公告)日：2012-03-29

    申请号：US12892465

    申请日：2010-09-28

    申请人： John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Kirk D. Peterson ,  Jed H. Rankin ,  Robert R. Robison

    发明人： John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Kirk D. Peterson ,  Jed H. Rankin ,  Robert R. Robison

    IPC分类号： H01L27/092 ,  H01L21/8238

    CPC分类号： H01L21/76879 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L27/092

    摘要： Disclosed herein are various methods and structures using contacts to create differential stresses on devices in an integrated circuit (IC) chip. An IC chip is disclosed having a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET), a PFET contact to a source/drain region of the PFET and an NFET contact to a source/drain region of the NFET. In a first embodiment, a silicon germanium (SiGe) layer is included only under the PFET contact, between the PFET contact and the source/drain region of the PFET. In a second embodiment, either the PFET contact extends into the source/drain region of the PFET or the NFET contact extends into the source/drain region of the NFET.

    摘要翻译： 这里公开了使用触点在集成电路（IC）芯片中的器件上产生差分应力的各种方法和结构。 公开了具有p型场效应晶体管（PFET）和n型场效应晶体管（NFET）的IC芯片，与PFET的源极/漏极区域的PFET接触以及与源极/漏极区域的NFET接触 的NFET。 在第一实施例中，在PFET接触和PFET的源极/漏极区之间仅包含PFET接触下的硅锗（SiGe）层。 在第二实施例中，PFET触点延伸到PFET的源极/漏极区域中，或者NFET触点延伸到NFET的源极/漏极区域。

    Methods for enhancing quality of pixel sensor image frames for global shutter imaging
    92.
    发明授权
    Methods for enhancing quality of pixel sensor image frames for global shutter imaging 有权
    用于提高全局快门成像的像素传感器图像帧质量的方法

    公开(公告)号：US08077240B2

    公开(公告)日：2011-12-13

    申请号：US12107825

    申请日：2008-04-23

    申请人： John J. Ellis-Monaghan ,  Mark D. Jaffe

    发明人： John J. Ellis-Monaghan ,  Mark D. Jaffe

    IPC分类号： H04N3/14 ,  H04N5/335 ,  H04N9/64 ,  H01L31/062 ,  H01L31/113

    CPC分类号： H04N5/361 ,  H04N5/359

    摘要： The image quality of an image frame from a CMOS image sensor array operated in global shutter mode may be enhanced by dispersing or randomizing the noise introduced by leakage currents from floating drains among the rows of the image frame. Further, the image quality may be improved by accounting for time dependent changes in the output of dark pixels in dark pixel rows or dark pixel columns. In addition, voltage and time dependent changes in the output of dark pixels may also be measured to provide an accurate estimate of the noise introduced to the charge held in the floating drains. Such methods may be employed individually or in combination to improve the quality of the image.

    摘要翻译： 来自在全球快门模式下操作的CMOS图像传感器阵列的图像帧的图像质量可以通过将来自浮动排水口的泄漏电流引入的噪声分散或随机化在图像帧的行中来增强。 此外，通过考虑暗像素行或暗像素列中的暗像素的输出中的时间依赖性变化，可以提高图像质量。 此外，还可以测量暗像素的输出中的电压和时间相关的变化，以提供引入到浮动排水管中的电荷的噪声的准确估计。 这样的方法可以单独使用或组合使用以提高图像的质量。

    Semiconductor wafer processing method that allows device regions to be selectively annealed following back end of the line (BEOL) metal wiring layer formation
    93.
    发明授权
    Semiconductor wafer processing method that allows device regions to be selectively annealed following back end of the line (BEOL) metal wiring layer formation 有权
    半导体晶片处理方法允许器件区域在线后面（BEOL）金属布线层形成之后被选择性地退火

    公开(公告)号：US08021950B1

    公开(公告)日：2011-09-20

    申请号：US12911940

    申请日：2010-10-26

    申请人： Wagdi W. Abadeer ,  Lilian Kamal, legal representative ,  John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Tom C. Lee

    发明人： Wagdi W. Abadeer ,  John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Tom C. Lee

    IPC分类号： H01L21/336

    CPC分类号： H01L21/28044 ,  H01L21/268 ,  H01L29/1054 ,  H01L29/4925 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

    摘要： Disclosed are embodiments of a semiconductor wafer processing method that allow device regions to be selectively annealed following back end of the line (BEOL) metal wiring formation without degrading wiring layer reliability. In the embodiments, a semiconductor device is formed adjacent to the top surface of a wafer such that it incorporates a selectively placed infrared absorbing layer (IAL). Then, following BEOL metal wiring formation, the bottom surface of the wafer is exposed to an infrared light having a wavelength that is transparent to the wafer. The infrared light is absorbed by and, thereby heats up the IAL to a first predetermined temperature (e.g., a dopant activation temperature, a temperature required for a state change, etc.). The resulting heat is transferred from the IAL to an adjacent region of the semiconductor device without raising the temperature of the metal wiring above a second predetermined temperature (e.g., a temperature that could degrade the metal wiring) that is lower than the first predetermined temperature.

    摘要翻译： 公开了允许器件区域在线路后端（BEOL）金属布线形成之后选择性退火的半导体晶片处理方法的实施例，而不会降低布线层的可靠性。 在实施例中，半导体器件形成为与晶片的顶表面相邻，使得其结合有选择放置的红外线吸收层（IAL）。 然后，在BEOL金属布线形成之后，晶片的底面暴露于对晶片透明的波长的红外光。 红外光被IAL吸收，从而将IAL加热到第一预定温度（例如，掺杂剂活化温度，状态改变所需的温度等）。 所产生的热量从IAL转移到半导体器件的相邻区域，而不会将金属布线的温度升高到低于第一预定温度的第二预定温度（例如，可能降低金属布线的温度）。

    VARIABLE DYNAMIC RANGE PIXEL SENSOR CELL, DESIGN STRUCTURE AND METHOD
    96.
    发明申请
    VARIABLE DYNAMIC RANGE PIXEL SENSOR CELL, DESIGN STRUCTURE AND METHOD 有权
    可变动态范围像素传感器单元，设计结构和方法

    公开(公告)号：US20100245644A1

    公开(公告)日：2010-09-30

    申请号：US12553457

    申请日：2009-09-03

    申请人： John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Charles F. Musante

    发明人： John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Charles F. Musante

    IPC分类号： H04N5/335 ,  H01L27/00

    CPC分类号： H04N5/37452 ,  H01L27/14609 ,  H04N5/35581 ,  H04N5/3575

    摘要： A pixel sensor cell including a column circuit, a design structure for fabricating the pixel sensor cell including the column circuit and a method for operating the pixel sensor cell including the column circuit are predicated upon the measurement of multiple reference data point and signal data point pairs from a floating diffusion at a variable capacitance. The variable capacitance is provided by excluding or including a transfer gate transistor capacitance in addition to a floating diffusion capacitance. Such a variable capacitance provides variable dynamic ranges for the pixel sensor cell including the column circuit.

    摘要翻译： 包括列电路的像素传感器单元，用于制造包括列电路的像素传感器单元的设计结构和用于操作包括列电路的像素传感器单元的方法基于多个参考数据点和信号数据点对的测量 从可变电容的浮动扩散。 通过排除或包括传输栅极晶体管电容以及浮动扩散电容来提供可变电容。 这种可变电容为包括列电路的像素传感器单元提供了可变的动态范围。

    CMOS IMAGER PHOTODIODE WITH ENHANCED CAPACITANCE
    97.
    发明申请
    CMOS IMAGER PHOTODIODE WITH ENHANCED CAPACITANCE 有权
    具有增强电容的CMOS IMAGER光电二极管

    公开(公告)号：US20100084690A1

    公开(公告)日：2010-04-08

    申请号：US12634898

    申请日：2009-12-10

    申请人： James W. Adkisson ,  John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Dale J. Pearson ,  Dennis L. Rogers

    发明人： James W. Adkisson ,  John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Dale J. Pearson ,  Dennis L. Rogers

    IPC分类号： H01L27/148 ,  H01L31/18

    CPC分类号： H01L27/14643 ,  H01L27/1463 ,  H01L27/14689 ,  H01L31/035281

    摘要： A pixel sensor cell having a semiconductor substrate having a surface; a photosensitive element formed in a substrate having a non-laterally disposed charge collection region entirely isolated from a physical boundary including the substrate surface. The photosensitive element comprises a trench having sidewalls formed in the substrate of a first conductivity type material; a first doped layer of a second conductivity type material formed adjacent to at least one of the sidewalls; and a second doped layer of the first conductivity type material formed between the first doped layer and the at least one trench sidewall and formed at a surface of the substrate, the second doped layer isolating the first doped layer from the at least one trench sidewall and the substrate surface. In a further embodiment, an additional photosensitive element is provided that includes a laterally disposed charge collection region that contacts the non-laterally disposed charge collection region of the photosensitive element and underlies the doped layer formed at the substrate surface.

    摘要翻译： 一种像素传感器单元，具有具有表面的半导体衬底; 形成在具有与包括基板表面的物理边界完全隔离的非横向布置的电荷收集区域的基板中的感光元件。 感光元件包括具有形成在第一导电类型材料的衬底中的侧壁的沟槽; 与所述侧壁中的至少一个相邻形成的第二导电类型材料的第一掺杂层; 以及形成在所述第一掺杂层和所述至少一个沟槽侧壁之间且形成在所述衬底的表面处的所述第一导电类型材料的第二掺杂层，所述第二掺杂层将所述第一掺杂层与所述至少一个沟槽侧壁隔离， 基材表面。 在另一个实施例中，提供附加的光敏元件，其包括横向设置的电荷收集区域，其接触感光元件的非横向设置的电荷收集区域，并且位于在衬底表面形成的掺杂层的下方。

    Silicide strapping in imager transfer gate device
    98.
    发明授权
    Silicide strapping in imager transfer gate device 有权
    成像器中的硅化物贴带传输门装置

    公开(公告)号：US07675097B2

    公开(公告)日：2010-03-09

    申请号：US11565801

    申请日：2006-12-01

    申请人： James W. Adkisson ,  John J. Ellis-Monaghan ,  R. Michael Guidash ,  Mark D. Jaffe ,  Edward T. Nelson ,  Richard J. Rassel ,  Charles V. Stancampiano

    发明人： James W. Adkisson ,  John J. Ellis-Monaghan ,  R. Michael Guidash ,  Mark D. Jaffe ,  Edward T. Nelson ,  Richard J. Rassel ,  Charles V. Stancampiano

    IPC分类号： H01L27/146

    CPC分类号： H01L27/14609 ,  H01L27/14643 ,  H01L27/14689

    摘要： A CMOS active pixel sensor (APS) cell structure having dual workfunction transfer gate device and method of fabrication. The transfer gate device comprises a dielectric layer formed on a substrate and a dual workfunction gate conductor layer formed on the dielectric layer comprising a first conductivity type doped region and an abutting second conductivity type doped region. The transfer gate device defines a channel region where charge accumulated by a photosensing device is transferred to a diffusion region. A silicide structure is formed atop the dual workfunction gate conductor layer for electrically coupling the first and second conductivity type doped regions. In one embodiment, the silicide contact is smaller in area dimension than an area dimension of said dual workfunction gate conductor layer. Presence of the silicide strap prevents the diodic behavior from allowing one or the other side of the gate to float to an indeterminate voltage.

    摘要翻译： 具有双功能转移栅极器件和制造方法的CMOS有源像素传感器（APS）单元结构。 传输栅极器件包括形成在衬底上的电介质层和形成在包括第一导电类型掺杂区和邻接第二导电类型掺杂区的电介质层上的双功函数栅导体层。 传输门装置限定了由光敏装置累积的电荷被传送到扩散区的沟道区。 在双功函数栅极导体层顶部形成硅化物结构，用于电耦合第一和第二导电类型掺杂区域。 在一个实施例中，硅化物接触面积尺寸小于所述双功函数栅极导体层的面积尺寸。 硅化物带的存在防止了双极性行为允许栅极的一侧或另一侧浮动到不确定的电压。

    PIXEL SENSOR CELL WITH FRAME STORAGE CAPABILITY
    99.
    发明申请
    PIXEL SENSOR CELL WITH FRAME STORAGE CAPABILITY 有权
    具有帧存储能力的像素传感器单元

    公开(公告)号：US20100013973A1

    公开(公告)日：2010-01-21

    申请号：US12174289

    申请日：2008-07-16

    申请人： James W. Adkisson ,  John J. Ellis-Monaghan ,  Rajendran Krishnasamy ,  Solomon Mulugeta ,  Charles F. Musante ,  Richard J. Rassel

    发明人： James W. Adkisson ,  John J. Ellis-Monaghan ,  Rajendran Krishnasamy ,  Solomon Mulugeta ,  Charles F. Musante ,  Richard J. Rassel

    IPC分类号： H04N5/335

    CPC分类号： H04N5/37452 ,  H04N5/2355

    摘要： A set of frame transfer transistors are provided between a hold gate transistor and a transfer gate transistor of a CMOS image sensor to enable storage of charge generate in the photosensitive diode after exposure. The readout of the charges from the set of frame transfer transistors may be performed after a plurality of exposures of the CMOS image sensor, between each of which charges are shifted toward the transfer gate transistor within the set of frame transfer transistors. Useful operation modes are enabled including a burst mode operation for rapid capture of successive images and high dynamic range operations in which multiple images are taken with different exposure times or a large capacitance is provided by ganging the diffusions of the set of frame transfer transistors.

    摘要翻译： 在CMOS图像传感器的保持栅晶体管和传输栅极晶体管之间提供一组帧传输晶体管，以便能够在曝光之后存储在感光二极管中产生的电荷。 可以在CMOS图像传感器的多次曝光之后，在每个帧转移晶体管中的每个电荷向着传输门晶体管移动之前执行来自该组帧转移晶体管的电荷的读出。 启用有用的操作模式，包括用于快速捕获连续图像的突发模式操作和其中以不同曝光时间拍摄多个图像的高动态范围操作，或者通过组合帧传输晶体管的扩散来提供大的电容。