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公开(公告)号：US08440998B2
公开(公告)日：2013-05-14
申请号：US12643848
申请日：2009-12-21
IPC分类号： H01L29/06
CPC分类号： H01L29/7783 , B82Y10/00 , H01L29/66431 , H01L29/66462 , H01L29/778 , H01L29/7781 , H01L29/7782 , H01L29/7785 , H01L29/7848 , H01L29/802 , H01L29/803
摘要： Embodiments of the present disclosure describe structures and techniques to increase carrier injection velocity for integrated circuit devices. An integrated circuit device includes a semiconductor substrate, a first barrier film coupled with the semiconductor substrate, a quantum well channel coupled to the first barrier film, the quantum well channel comprising a first material having a first bandgap energy, and a source structure coupled to launch mobile charge carriers into the quantum well channel, the source structure comprising a second material having a second bandgap energy, wherein the second bandgap energy is greater than the first bandgap energy. Other embodiments may be described and/or claimed.
摘要翻译： 本公开的实施例描述了用于增加集成电路器件的载流子注入速度的结构和技术。 集成电路器件包括半导体衬底，与半导体衬底耦合的第一阻挡膜，耦合到第一阻挡膜的量子阱沟道，该量子阱沟道包括具有第一带隙能量的第一材料和耦合到 将移动电荷载流子发射到量子阱沟道中，源结构包括具有第二带隙能量的第二材料，其中第二带隙能量大于第一带隙能量。 可以描述和/或要求保护其他实施例。
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公开(公告)号：US20120153263A1
公开(公告)日：2012-06-21
申请号：US12972057
申请日：2010-12-17
IPC分类号： H01L29/15
CPC分类号： H01L29/7391 , H01L29/0843
摘要： The present disclosure relates to the field of microelectronic transistor fabrication and, more particularly, to the fabrication of a tunnel field effect transistor having an improved on-current level without a corresponding increasing the off-current level, achieved by the addition of a transition layer between a source and an intrinsic channel of the tunnel field effect transistor.
摘要翻译： 本公开涉及微电子晶体管制造领域，更具体地说，涉及具有改善的导通电流水平的隧道场效应晶体管的制造，而不相应地增加截止电流水平，通过添加过渡层 在隧道场效应晶体管的源极和固有沟道之间。
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公开(公告)号：US20110147708A1
公开(公告)日：2011-06-23
申请号：US12643848
申请日：2009-12-21
IPC分类号： H01L29/66 , H01L29/778 , H01L21/335
CPC分类号： H01L29/7783 , B82Y10/00 , H01L29/66431 , H01L29/66462 , H01L29/778 , H01L29/7781 , H01L29/7782 , H01L29/7785 , H01L29/7848 , H01L29/802 , H01L29/803
摘要： Embodiments of the present disclosure describe structures and techniques to increase carrier injection velocity for integrated circuit devices. An integrated circuit device includes a semiconductor substrate, a first barrier film coupled with the semiconductor substrate, a quantum well channel coupled to the first barrier film, the quantum well channel comprising a first material having a first bandgap energy, and a source structure coupled to launch mobile charge carriers into the quantum well channel, the source structure comprising a second material having a second bandgap energy, wherein the second bandgap energy is greater than the first bandgap energy. Other embodiments may be described and/or claimed.
摘要翻译： 本公开的实施例描述了用于增加集成电路器件的载流子注入速度的结构和技术。 集成电路器件包括半导体衬底，与半导体衬底耦合的第一阻挡膜，耦合到第一阻挡膜的量子阱沟道，该量子阱沟道包括具有第一带隙能量的第一材料和耦合到 将移动电荷载流子发射到量子阱沟道中，源结构包括具有第二带隙能量的第二材料，其中第二带隙能量大于第一带隙能量。 可以描述和/或要求保护其他实施例。
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公开(公告)号：US07777282B2
公开(公告)日：2010-08-17
申请号：US12228457
申请日：2008-08-13
CPC分类号： H01L21/26586 , H01L21/2652 , H01L29/66545 , H01L29/7835
摘要： A microelectronic device includes a tunneling pocket within an asymmetrical semiconductive body including source- and drain wells. The tunneling pocket is formed by a self-aligned process by removing a dummy gate electrode from a gate spacer and by implanting the tunneling pocket into the semiconductive body or into an epitaxial film that is part of the semiconductive body.
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95.发明申请Self-aligned tunneling pocket in field-effect transistors and processes to form same 有权在场效应晶体管中的自对准隧道口和形成相同的工艺公开(公告)号：US20100038713A1
公开(公告)日：2010-02-18
申请号：US12228457
申请日：2008-08-13
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/26586 , H01L21/2652 , H01L29/66545 , H01L29/7835
摘要： A microelectronic device includes a tunneling pocket within an asymmetrical semiconductive body including source- and drain wells. The tunneling pocket is formed by a self-aligned process by removing a dummy gate electrode from a gate spacer and by implanting the tunneling pocket into the semiconductive body or into an epitaxial film that is part of the semiconductive body.
摘要翻译： 微电子器件包括位于不对称半导体内的隧道槽，其包括源阱和漏极井。 通过从栅极隔离物去除虚拟栅极电极并且将隧穿槽注入半导体本体或者作为半导体本体的一部分的外延膜中，通过自对准工艺形成隧穿袋。
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公开(公告)号：US20120032146A1
公开(公告)日：2012-02-09
申请号：US13274468
申请日：2011-10-17
CPC分类号： H01L29/66977 , H01L29/1083 , H01L29/161 , H01L29/365 , H01L29/66431 , H01L29/66439 , H01L29/7781
摘要： Embodiments of an apparatus and methods of providing a quantum well device for improved parallel conduction are generally described herein. Other embodiments may be described and claimed.
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97.发明申请DOUBLE PASS FORMATION OF A DEEP QUANTUM WELL IN ENHANCEMENT MODE III-V DEVICES 有权增强型III-V器件中的深度质量的双重通道形成公开(公告)号：US20100163849A1
公开(公告)日：2010-07-01
申请号：US12347925
申请日：2008-12-31
IPC分类号： H01L29/12 , H01L21/336 , G03F7/20
CPC分类号： H01L29/0847 , B82Y10/00 , H01L29/122 , H01L29/4236 , H01L29/452 , H01L29/475 , H01L29/517 , H01L29/66462 , H01L29/7783
摘要： A quantum well is formed for a deep well III-V semiconductor device using double pass patterning. In one example, the well is formed by forming a first photolithography pattern over terminals on a material stack, etching a well between the terminals using the first photolithography patterning, removing the first photolithography pattern, forming a second photolithography pattern over the terminals and at least a portion of the well, deepening the well between the terminals by etching using the second photolithography pattern, removing the second photolithography pattern, and finishing the terminals and the well to form a device on the material stack.
摘要翻译： 对于使用双向图案化的深阱III-V半导体器件形成量子阱。 在一个示例中，孔通过在材料堆叠上的端子上形成第一光刻图案，使用第一光刻图案蚀刻端子之间的阱，去除第一光刻图案，在端子上形成第二光刻图案，并且至少 通过使用第二光刻图案的蚀刻，去除第二光刻图案，以及完成端子和阱以在材料堆叠上形成器件，从而使端子之间的阱深化，从而使端子之间的阱加深。
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98.发明授权Tunneling field effect transistors (TFETs) for CMOS approaches to fabricating N-type and P-type TFETs 有权用于CMOS方法的隧道场效应晶体管（TFET）用于制造N型和P型TFET公开(公告)号：US08890120B2
公开(公告)日：2014-11-18
申请号：US13678867
申请日：2012-11-16
申请人： Roza Kotlyar , Stephen M. Cea , Gilbert Dewey , Benjamin Chu-Kung , Uygar E. Avci , Rafael Rios , Anurag Chaudhry , Thomas D. Linton, Jr. , Ian A. Young , Kelin J. Kuhn
发明人： Roza Kotlyar , Stephen M. Cea , Gilbert Dewey , Benjamin Chu-Kung , Uygar E. Avci , Rafael Rios , Anurag Chaudhry , Thomas D. Linton, Jr. , Ian A. Young , Kelin J. Kuhn
CPC分类号： H01L29/66977 , H01L27/092 , H01L29/045 , H01L29/0676 , H01L29/068 , H01L29/1054 , H01L29/16 , H01L29/161 , H01L29/165 , H01L29/20 , H01L29/24 , H01L29/267 , H01L29/42392 , H01L29/7391 , H01L29/7842 , H01L29/785 , H01L29/78603 , H01L29/78642 , H01L29/78684 , H01L29/78696
摘要： Tunneling field effect transistors (TFETs) for CMOS architectures and approaches to fabricating N-type and P-type TFETs are described. For example, a tunneling field effect transistor (TFET) includes a homojunction active region disposed above a substrate. The homojunction active region includes a relaxed Ge or GeSn body having an undoped channel region therein. The homojunction active region also includes doped source and drain regions disposed in the relaxed Ge or GeSn body, on either side of the channel region. The TFET also includes a gate stack disposed on the channel region, between the source and drain regions. The gate stack includes a gate dielectric portion and gate electrode portion.
摘要翻译： 描述了用于CMOS架构的隧道场效应晶体管（TFET）和制造N型和P型TFET的方法。 例如，隧道场效应晶体管（TFET）包括设置在衬底上方的均质有源区。 同质结有源区包括其中具有未掺杂沟道区的松弛Ge或GeSn体。 同质结有源区还包括设置在放大的Ge或GeSn体中，在沟道区两侧的掺杂源极和漏极区。 TFET还包括设置在沟道区域之间的源极和漏极区域之间的栅极堆叠。 栅极堆叠包括栅极电介质部分和栅极电极部分。
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99.发明授权Tunneling field effect transistors (TFETs) for CMOS architectures and approaches to fabricating N-type and P-type TFETs 有权用于CMOS架构的隧道场效应晶体管（TFET）和制造N型和P型TFET的方法公开(公告)号：US09583602B2
公开(公告)日：2017-02-28
申请号：US15209552
申请日：2016-07-13
申请人： Roza Kotlyar , Stephen M. Cea , Gilbert Dewey , Benjamin Chu-Kung , Uygar E. Avci , Rafael Rios , Anurag Chaudhry , Thomas D. Linton, Jr. , Ian A. Young , Kelin J. Kuhn
发明人： Roza Kotlyar , Stephen M. Cea , Gilbert Dewey , Benjamin Chu-Kung , Uygar E. Avci , Rafael Rios , Anurag Chaudhry , Thomas D. Linton, Jr. , Ian A. Young , Kelin J. Kuhn
IPC分类号： H01L29/66 , H01L29/78 , H01L29/739 , H01L29/16 , H01L29/161 , H01L29/06 , H01L29/24 , H01L29/267 , H01L27/092 , H01L29/04 , H01L29/10 , H01L29/165 , H01L29/20 , H01L29/423 , H01L29/786
CPC分类号： H01L29/66977 , H01L27/092 , H01L29/045 , H01L29/0676 , H01L29/068 , H01L29/1054 , H01L29/16 , H01L29/161 , H01L29/165 , H01L29/20 , H01L29/24 , H01L29/267 , H01L29/42392 , H01L29/7391 , H01L29/7842 , H01L29/785 , H01L29/78603 , H01L29/78642 , H01L29/78684 , H01L29/78696
摘要： Tunneling field effect transistors (TFETs) for CMOS architectures and approaches to fabricating N-type and P-type TFETs are described. For example, a tunneling field effect transistor (TFET) includes a homojunction active region disposed above a substrate. The homojunction active region includes a relaxed Ge or GeSn body having an undoped channel region therein. The homojunction active region also includes doped source and drain regions disposed in the relaxed Ge or GeSn body, on either side of the channel region. The TFET also includes a gate stack disposed on the channel region, between the source and drain regions. The gate stack includes a gate dielectric portion and gate electrode portion.
摘要翻译： 描述了用于CMOS架构的隧道场效应晶体管（TFET）和制造N型和P型TFET的方法。 例如，隧道场效应晶体管（TFET）包括设置在衬底上方的均质有源区。 同质结有源区包括其中具有未掺杂沟道区的松弛Ge或GeSn体。 同质结有源区还包括设置在放大的Ge或GeSn体中，在沟道区两侧的掺杂源极和漏极区。 TFET还包括设置在沟道区域之间的源极和漏极区域之间的栅极堆叠。 栅极堆叠包括栅极电介质部分和栅极电极部分。
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100.发明申请公开(公告)号：US20160322480A1
公开(公告)日：2016-11-03
申请号：US15209552
申请日：2016-07-13
申请人： Roza Kotlyar , Stephen M. Cea , Gilbert Dewey , Benjamin Chu-Kung , Uygar E. Avci , Rafael Rios , Anurag Chaudhry , Thomas D. Linton, JR. , Ian A. Young , Kelin J. Kuhn
发明人： Roza Kotlyar , Stephen M. Cea , Gilbert Dewey , Benjamin Chu-Kung , Uygar E. Avci , Rafael Rios , Anurag Chaudhry , Thomas D. Linton, JR. , Ian A. Young , Kelin J. Kuhn
IPC分类号： H01L29/66 , H01L29/06 , H01L29/165 , H01L27/092 , H01L29/161 , H01L29/10 , H01L29/20 , H01L29/04 , H01L29/786 , H01L29/423
CPC分类号： H01L29/66977 , H01L27/092 , H01L29/045 , H01L29/0676 , H01L29/068 , H01L29/1054 , H01L29/16 , H01L29/161 , H01L29/165 , H01L29/20 , H01L29/24 , H01L29/267 , H01L29/42392 , H01L29/7391 , H01L29/7842 , H01L29/785 , H01L29/78603 , H01L29/78642 , H01L29/78684 , H01L29/78696
摘要： Tunneling field effect transistors (TFETs) for CMOS architectures and approaches to fabricating N-type and P-type TFETs are described. For example, a tunneling field effect transistor (TFET) includes a homojunction active region disposed above a substrate. The homojunction active region includes a relaxed Ge or GeSn body having an undoped channel region therein. The homojunction active region also includes doped source and drain regions disposed in the relaxed Ge or GeSn body, on either side of the channel region. The TFET also includes a gate stack disposed on the channel region, between the source and drain regions. The gate stack includes a gate dielectric portion and gate electrode portion.
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