公开(公告)号：US20090039416A1

公开(公告)日：2009-02-12

申请号：US11845321

申请日：2007-08-27

申请人： Sheng Chih Lai ,  Hang-Ting Lue ,  Chien Wei Liao

发明人： Sheng Chih Lai ,  Hang-Ting Lue ,  Chien Wei Liao

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L27/115 ,  G11C16/0466 ,  G11C16/0483 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/513 ,  H01L29/792

摘要： A band gap engineered, charge trapping memory cell includes a charge trapping element that is separated from a gate by a blocking layer of metal doped silicon oxide material having a medium dielectric constant, such as aluminum doped silicon oxide, and separated from the semiconductor body including the channel by an engineered tunneling dielectric.

摘要翻译： 带隙设计的电荷捕获存储单元包括电荷捕获元件，其通过具有介电常数的金属掺杂氧化硅材料的阻挡层（例如掺铝氧化硅）与栅极分离，并与半导体本体分离，包括 通道由工程隧道电介质。

公开(公告)号：US07391652B2

公开(公告)日：2008-06-24

申请号：US11381760

申请日：2006-05-05

申请人： Hang-Ting Lue

发明人： Hang-Ting Lue

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C16/0466 ,  G11C16/12 ,  G11C16/3418 ,  G11C16/3427

摘要： A programming method for a p-channel memory cell, the memory cell includes a source, a drain and a gate. The gate is applies with a first voltage, which results in Fowler-Nordheim (−FN) hole injection, thereby causing the memory cell to be in a programmed state.

摘要翻译： 一种用于p沟道存储单元的编程方法，所述存储单元包括源极，漏极和栅极。 门施加第一电压，这导致Fowler-Nordheim（-FN）空穴注入，从而使存储器单元处于编程状态。

公开(公告)号：US20080116506A1

公开(公告)日：2008-05-22

申请号：US11756559

申请日：2007-05-31

申请人： Hang-Ting Lue

发明人： Hang-Ting Lue

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/788 ,  H01L29/792

摘要： A memory cell comprising: a semiconductor substrate with a surface with a source region and a drain region disposed below the surface of the substrate and separated by a channel region; a tunneling barrier dielectric structure with an effective oxide thickness of greater than 3 nanometers disposed above the channel region; a conductive layer disposed above the tunneling barrier dielectric structure and above the channel region; a charge trapping structure disposed above the conductive layer and above the channel region; a top dielectric structure disposed above the charge trapping structure and above the channel region; and a top conductive layer disposed above the top dielectric structure and above the channel region are described along with devices thereof and methods for manufacturing.

摘要翻译： 一种存储单元，包括：具有表面的半导体衬底，源极区和漏极区设置在衬底的表面下方并被沟道区分开; 设置在沟道区域上方的具有大于3纳米的有效氧化物厚度的隧道势垒介电结构; 导电层，设置在隧道势垒电介质结构之上并在沟道区之上; 电荷捕获结构，设置在导电层之上并在沟道区上方; 位于所述电荷俘获结构上方且位于所述沟道区上方的顶部电介质结构; 以及设置在顶部电介质结构之上和沟道区上方的顶部导电层以及其制造方法和制造方法。

公开(公告)号：US20080087942A1

公开(公告)日：2008-04-17

申请号：US11785322

申请日：2007-04-17

申请人： Tzu-Hsuan Hsu ,  Hang-Ting Lue

发明人： Tzu-Hsuan Hsu ,  Hang-Ting Lue

IPC分类号： H01L29/792 ,  G11C11/34 ,  H01L21/336

CPC分类号： H01L29/66833 ,  G11C16/0466 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/785 ,  H01L29/792

摘要： A vertical channel memory including a substrate, a channel, a multi-layer structure, a gate, a first terminal and a second terminal is provided. The channel is protruded from the substrate and has a top surface and two vertical surfaces. The multi-layer structure is disposed on the two vertical surfaces of the channel. The gate straddling multi-layer structure is positioned above the two vertical surfaces of the channel. The first terminal and the second terminal are respectively positioned at two sides of the channel opposing to the gate.

摘要翻译： 提供了包括基板，通道，多层结构，栅极，第一端子和第二端子的垂直沟道存储器。 通道从基板突出并具有顶表面和两个垂直表面。 多层结构设置在通道的两个垂直表面上。 栅极跨层多层结构位于通道的两个垂直表面上方。 第一端子和第二端子分别位于与栅极相对的通道的两侧。

公开(公告)号：US20080079064A1

公开(公告)日：2008-04-03

申请号：US11898528

申请日：2007-09-13

申请人： Sheng-Chih Lai ,  Hang-Ting Lue

发明人： Sheng-Chih Lai ,  Hang-Ting Lue

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L29/517 ,  H01L29/513 ,  H01L29/66833 ,  H01L29/792

摘要： A semiconductor device having a non-volatile memory and a method of manufacturing the same are provided. The semiconductor device includes a base material and a stack structure. The stack structure disposed on the base material at least includes a tunneling layer, a trapping layer and a dielectric layer. The trapping layer is disposed on the tunneling layer. The dielectric layer has a dielectric constant and is disposed on the trapping layer. The dielectric layer is transformed from a first solid state to a second solid state when the dielectric layer undergoes a process.

摘要翻译： 提供了具有非易失性存储器的半导体器件及其制造方法。 半导体器件包括基底材料和堆叠结构。 设置在基材上的堆叠结构至少包括隧穿层，捕获层和电介质层。 捕获层设置在隧道层上。 电介质层具有介电常数并且设置在捕获层上。 当电介质层进行处理时，电介质层从第一固态转变为第二固态。

公开(公告)号：US07315474B2

公开(公告)日：2008-01-01

申请号：US11324581

申请日：2006-01-03

申请人： Hang-Ting Lue

发明人： Hang-Ting Lue

IPC分类号： G11C11/34

CPC分类号： H01L29/792 ,  G11C16/0483 ,  G11C16/0491 ,  H01L21/265 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/66833

摘要： Memory cells comprising: a semiconductor substrate having a source region and a drain region disposed below a surface of the substrate and separated by a channel region; a tunnel dielectric structure disposed above the channel region, the tunnel dielectric structure comprising at least one layer having a small hole-tunneling-barrier height; a charge storage layer disposed above the tunnel dielectric structure; an insulating layer disposed above the charge storage layer; and a gate electrode disposed above the insulating layer are described along with arrays thereof and methods of operation.

摘要翻译： 存储单元包括：半导体衬底，其具有设置在衬底的表面下方并由沟道区分隔开的源极区和漏极区; 隧道电介质结构，其设置在所述沟道区上方，所述隧道介电结构包括至少一层具有小的空穴隧道势垒高度的层; 设置在隧道介电结构上方的电荷存储层; 设置在电荷存储层上方的绝缘层; 并且描述设置在绝缘层上方的栅极电极及其阵列和操作方法。

公开(公告)号：US20070258289A1

公开(公告)日：2007-11-08

申请号：US11381760

申请日：2006-05-05

申请人： Hang-Ting Lue

发明人： Hang-Ting Lue

IPC分类号： G11C16/04 ,  G11C16/06 ,  G11C11/34

CPC分类号： G11C16/0483 ,  G11C16/0466 ,  G11C16/12 ,  G11C16/3418 ,  G11C16/3427

摘要： A programming method for a p-channel memory cell, the memory cell includes a source, a drain and a gate. The gate is applies with a first voltage, which results in Fowler-Nordheim (−FN) hole injection, thereby causing the memory cell to be in a programmed state.

摘要翻译： 一种用于p沟道存储单元的编程方法，所述存储单元包括源极，漏极和栅极。 门施加第一电压，这导致Fowler-Nordheim（-FN）空穴注入，从而使存储器单元处于编程状态。

公开(公告)号：US09082656B2

公开(公告)日：2015-07-14

申请号：US13294852

申请日：2011-11-11

申请人： Shih-Hung Chen ,  Hang-Ting Lue ,  Yen-Hao Shih

发明人： Shih-Hung Chen ,  Hang-Ting Lue ,  Yen-Hao Shih

IPC分类号： H01L27/115

CPC分类号： H01L27/1157 ,  H01L27/11578

摘要： A manufacturing method for a memory array includes first forming a multilayer stack of dielectric material on a plurality of semiconductor strips, and then exposing the multilayer stack in switch transistor regions. The multilayer stacks exposed in the switch transistor regions are processed to form gate dielectric structures that are different than the dielectric charge trapping structures. Word lines and select lines are then formed. A 3D array of dielectric charge trapping memory cells includes stacks of NAND strings of memory cells. A plurality of switch transistors are coupled to the NAND strings, the switch transistors including gate dielectric structures wherein the gate dielectric structures are different than the dielectric charge trapping structures.

摘要翻译： 一种用于存储器阵列的制造方法包括首先在多个半导体条上形成多层电介质材料，然后在开关晶体管区域中暴露多层叠层。 在开关晶体管区域中暴露的多层堆叠被处理以形成不同于介电电荷俘获结构的栅介质结构。 然后形成字线和选择线。 介质电荷俘获存储器单元的3D阵列包括存储器单元的NAND串的堆叠。 多个开关晶体管耦合到NAND串，开关晶体管包括栅极电介质结构，其中栅极电介质结构不同于介电电荷俘获结构。

公开(公告)号：US08951862B2

公开(公告)日：2015-02-10

申请号：US13347331

申请日：2012-01-10

申请人： Shih-Hung Chen ,  Hang-Ting Lue ,  Yen-Hao Shih

发明人： Shih-Hung Chen ,  Hang-Ting Lue ,  Yen-Hao Shih

IPC分类号： H01L21/336

CPC分类号： H01L27/11582 ,  H01L29/7926

摘要： The technology relates to a damascene word line for a three dimensional array of nonvolatile memory cells. Conductive lines such as silicon are formed over stacked nonvolatile memory structures. Word line trenches separate neighboring ones of the silicon lines. The silicon lines separated by the word line trenches are oxidized, making insulating surfaces in the word line trenches. Word lines are made in the word line trenches.

摘要翻译： 该技术涉及用于非易失性存储器单元的三维阵列的大马士革字线。 诸如硅的导电线形成在堆叠的非易失性存储器结构之上。 字线沟槽分离出相邻的硅线。 由字线沟槽分隔的硅线被氧化，在字线沟槽中形成绝缘表面。 字线是在字线沟中制作的。

公开(公告)号：US08861273B2

公开(公告)日：2014-10-14

申请号：US12427587

申请日：2009-04-21

申请人： Hang-Ting Lue

发明人： Hang-Ting Lue

IPC分类号： G11C16/04 ,  H01L21/28 ,  H01L29/423 ,  H01L27/115 ,  H01L29/51

CPC分类号： H01L21/28282 ,  G11C16/0433 ,  H01L27/11565 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/513

摘要： A 2T cell NOR architecture based on the use of BE-SONOS for embedded memory includes memory cells having respective access transistors having access gates and memory transistors having memory gates arranged in series between the corresponding bit lines and one of the plural reference lines. A memory transistor in a memory cell comprises a semiconductor body including a channel having a channel surface and a charge storing dielectric stack between the memory gate and the channel surface. The dielectric stack comprises a bandgap engineered, tunneling dielectric layer contacting one of the gate (for gate injection tunneling) and the channel surface (for channel injection tunneling). The dielectric stack of the memory cell also includes a charge trapping dielectric layer on the tunneling dielectric layer and a blocking dielectric layer.

摘要翻译： 基于对嵌入式存储器使用BE-SONOS的2T单元NOR架构包括具有存取晶体管的存储单元，存储晶体管具有存取栅极和存储晶体管，存储晶体管具有串联布置在相应的位线和多条参考线之一中的存储栅极。 存储单元中的存储晶体管包括半导体本体，其包括具有沟道表面的沟道和在存储器栅极和沟道表面之间的电荷存储电介质叠层。 电介质堆叠包括接触栅极（用于栅极注入隧道）和沟道表面之一（用于沟道注入隧道）的带隙工程化的隧道电介质层。 存储单元的电介质叠层还包括在隧道介电层上的电荷捕获电介质层和阻挡电介质层。