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    Semiconductor chip with gate dielectrics for high-performance and low-leakage applications
    91.
    发明授权
    Semiconductor chip with gate dielectrics for high-performance and low-leakage applications 有权
    具有栅极电介质的半导体芯片，用于高性能和低漏电应用

    公开(公告)号：US06906398B2

    公开(公告)日：2005-06-14

    申请号：US10335962

    申请日：2003-01-02

    申请人： Yee-Chia Yeo ,  Fu-Liang Yang ,  Chenming Hu

    发明人： Yee-Chia Yeo ,  Fu-Liang Yang ,  Chenming Hu

    IPC分类号： H01L21/8234 ,  H01L27/088 ,  H01L29/72

    CPC分类号： H01L21/823462 ,  H01L27/088

    摘要： Both high performance and low leakage current devices can be formed on a single wafer without significant additional processing steps by the formation of an ultra-thin gate dielectric and a high-permittivity gate dielectric, respectively, in regions wherein switching speed and low leakage current, respectively, are desired. Logic and embedded memory regions can be performance optimized on the same integrated circuit.

    摘要翻译： 可以在单个晶片上形成高性能和低漏电流器件，而无需明显的附加处理步骤，即在其中开关速度和低漏电流的区域中分别形成超薄栅极电介质和高电容率栅极电介质， 分别是期望的。 逻辑和嵌入式存储器区域可以在同一集成电路上进行性能优化。

    Relaxed silicon germanium substrate with low defect density
    93.
    发明授权
    Relaxed silicon germanium substrate with low defect density 有权
    具有低缺陷密度的松弛硅锗衬底

    公开(公告)号：US06878610B1

    公开(公告)日：2005-04-12

    申请号：US10228545

    申请日：2002-08-27

    申请人： Chun Chich Lin ,  Yee-Chia Yeo ,  Chien-Chao Huang ,  Chao-Hsiung Wang ,  Tien-Chih Chang ,  Chenming Hu ,  Fu-Liang Yang ,  Shih-Chang Chen ,  Mong-Song Liang ,  Liang-Gi Yao

    发明人： Chun Chich Lin ,  Yee-Chia Yeo ,  Chien-Chao Huang ,  Chao-Hsiung Wang ,  Tien-Chih Chang ,  Chenming Hu ,  Fu-Liang Yang ,  Shih-Chang Chen ,  Mong-Song Liang ,  Liang-Gi Yao

    IPC分类号： C30B1/00 ,  H01L21/00 ,  H01L21/20 ,  H01L21/205 ,  H01L21/324 ,  H01L21/36 ,  H01L21/84 ,  H01L29/10

    CPC分类号： H01L29/1054 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/02532 ,  H01L21/324

    摘要： A method of forming a strained silicon layer on a relaxed, low defect density semiconductor alloy layer such as SiGe, has been developed. In a first embodiment of this invention the relaxed, low density SiGe layer is epitaxially grown on an silicon layer which in turn is located on an underlying SiGe layer. During the epitaxial growth of the overlying SiGe layer defects are formed in the underlying silicon layer resulting in the desired, relaxation, and decreased defect density for the SiGe layer. A second embodiment features an anneal procedure performed during growth of the relaxed SiGe layer, resulting in additional relaxation and decreased defect density, while a third embodiment features an anneal procedure performed to the underlying silicon layer prior to epitaxial growth of the relaxed SiGe layer, again allowing optimized relaxation and defect density to be realized for the SiGe layer. The ability to obtain a strained silicon layer on a relaxed, low defect density SiGe layer, allows devices with enhanced carrier mobility to be formed in the surface of the strained silicon layer, with decreased risk of leakage due the presence of the underlying, relaxed, low defect density SiGe layer.

    摘要翻译： 已经开发了在松弛的低缺陷密度半导体合金层如SiGe上形成应变硅层的方法。 在本发明的第一实施例中，松散的低密度SiGe层在硅层上外延生长，硅层又位于下面的SiGe层上。 在覆盖SiGe层的外延生长期间，在下层硅层中形成缺陷，导致SiGe层所需的，松弛的和降低的缺陷密度。 第二个实施例的特征在于在松弛的SiGe层的生长期间执行的退火程序，导致附加的松弛和降低的缺陷密度，而第三实施例的特征在于在弛豫的SiGe层的外延生长之前对下面的硅层进行退火处理 允许为SiGe层实现优化的弛豫和缺陷密度。 在松弛的低缺陷密度SiGe层上获得应变硅层的能力允许在应变硅层的表面形成具有增强的载流子迁移率的器件，由于存在下面的，放松的， 低缺陷密度SiGe层。

    Method of forming a transistor with a strained channel
    95.
    发明授权
    Method of forming a transistor with a strained channel 有权
    形成具有应变通道的晶体管的方法

    公开(公告)号：US06492216B1

    公开(公告)日：2002-12-10

    申请号：US10068926

    申请日：2002-02-07

    申请人： Yee-Chia Yeo ,  Fu-Liang Yang ,  Chenming Hu

    发明人： Yee-Chia Yeo ,  Fu-Liang Yang ,  Chenming Hu

    IPC分类号： H01L21336

    CPC分类号： H01L29/66636 ,  H01L29/1054 ,  H01L29/41783 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/7834 ,  H01L29/7842

    摘要： A method of forming a tensile or compressive strained channel region for a semiconductor device, such as a MOSFET device, allowing improved carrier transport properties and increased device performance to be realized, has been developed. The method features the epitaxial growth of a semiconductor layer such as silicon, or silicon-germanium, with the incorporation of atoms such as carbon. The silicon-germanium-carbon channel layer, under biaxial tensile or compressive strain, is then overlaid with an optional silicon capping layer, used to accommodate the overlying, thermally grown silicon dioxide gate insulator layer, of the MOSFET device.

    摘要翻译： 已经开发了形成用于诸如MOSFET器件的半导体器件的拉伸或压缩应变通道区域的方法，其允许改进的载流子传输特性和提高的器件性能得以实现。 该方法的特征在于诸如硅或硅 - 锗的半导体层的外延生长，其中引入诸如碳的原子。 然后，在双轴拉伸或压缩应变下的硅 - 锗 - 碳通道层覆盖有用于容纳MOSFET器件的上覆的热生长二氧化硅栅极绝缘体层的任选的硅封盖层。

    Multiple-gate transistors formed on bulk substrates
    96.
    发明授权
    Multiple-gate transistors formed on bulk substrates 有权
    形成在大量衬底上的多栅极晶体管

    公开(公告)号：US07863674B2

    公开(公告)日：2011-01-04

    申请号：US11645419

    申请日：2006-12-26

    申请人： Yee-Chia Yeo ,  Fu-Liang Yang ,  Chenming Hu

    发明人： Yee-Chia Yeo ,  Fu-Liang Yang ,  Chenming Hu

    IPC分类号： H01L31/062

    CPC分类号： H01L29/66795 ,  H01L29/42384 ,  H01L29/66818 ,  H01L29/7851 ,  H01L29/7853 ,  H01L2029/7857

    摘要： In one aspect, the present invention teaches a multiple-gate transistor 130 that includes a semiconductor fin 134 formed in a portion of a bulk semiconductor substrate 132. A gate dielectric 144 overlies a portion of the semiconductor fin 134 and a gate electrode 146 overlies the gate dielectric 144. A source region 138 and a drain region 140 are formed in the semiconductor fin 134 oppositely adjacent the gate electrode 144. In the preferred embodiment, the bottom surface 150 of the gate electrode 146 is lower than either the source-substrate junction 154 or the drain-substrate junction 152.

    摘要翻译： 在一个方面，本发明教导了一种多栅极晶体管130，其包括形成在体半导体衬底132的一部分中的半导体鳍片134.栅极电介质144覆盖在半导体鳍片134的一部分上，栅电极146覆盖 栅极电介质144.源极区域138和漏极区域140形成在与栅电极144相对的半导体鳍片134中。在优选实施例中，栅电极146的底表面150比源 - 154或漏极 - 衬底接合部152。

    Semiconductor-on-insulator SRAM configured using partially-depleted and fully-depleted transistors
    97.
    发明授权
    Semiconductor-on-insulator SRAM configured using partially-depleted and fully-depleted transistors 有权
    使用部分耗尽和完全耗尽的晶体管配置的绝缘体上半导体SRAM

    公开(公告)号：US07301206B2

    公开(公告)日：2007-11-27

    申请号：US10700869

    申请日：2003-11-04

    申请人： Yee-Chia Yeo ,  Fu-Liang Yang ,  Chenming Hu

    发明人： Yee-Chia Yeo ,  Fu-Liang Yang ,  Chenming Hu

    IPC分类号： H01I29/76

    CPC分类号： H01L27/1104 ,  H01L21/845 ,  H01L27/11 ,  H01L27/1211 ,  H01L29/7854

    摘要： A static memory element includes a first inverter having an input coupled to a left bit node and an output coupled to a right bit node. A second inverter has an input coupled to the right bit node and an output coupled to the left right bit node. A first fully depleted semiconductor-on-insulator transistor has a drain coupled to the left bit node, and a second fully depleted semiconductor-on-insulator transistor has a drain coupled to the right bit node.

    摘要翻译： 静态存储元件包括具有耦合到左位节点的输入和耦合到右位节点的输出的第一反相器。 第二反相器具有耦合到右位节点的输入和耦合到左右位节点的输出。 第一完全耗尽的绝缘体上半导体晶体管具有耦合到左位节点的漏极，并且第二完全耗尽的绝缘体上半导体晶体管具有耦合到右位节点的漏极。

    Methods and Structures for Planar and Multiple-Gate Transistors Formed on SOI
    99.
    发明申请
    Methods and Structures for Planar and Multiple-Gate Transistors Formed on SOI 有权
    在SOI上形成的平面和多栅极晶体管的方法和结构

    公开(公告)号：US20070134860A1

    公开(公告)日：2007-06-14

    申请号：US11676480

    申请日：2007-02-19

    申请人： Fu-Liang Yang ,  Yee-Chia Yeo ,  Chenming Hu

    发明人： Fu-Liang Yang ,  Yee-Chia Yeo ,  Chenming Hu

    IPC分类号： H01L21/84

    CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7854

    摘要： A semiconductor device includes an insulator layer, a semiconductor layer, a first transistor, and a second transistor. The semiconductor layer is overlying the insulator layer. A first portion of the semiconductor layer has a first thickness. A second portion of the semiconductor layer has a second thickness. The second thickness is larger than the first thickness. The first transistor has a first active region formed from the first portion of the semiconductor layer. The second transistor has a second active region formed from the second portion of the semiconductor layer. The first transistor may be a planar transistor and the second transistor may be a multiple-gate transistor, for example.

    摘要翻译： 半导体器件包括绝缘体层，半导体层，第一晶体管和第二晶体管。 半导体层覆盖绝缘体层。 半导体层的第一部分具有第一厚度。 半导体层的第二部分具有第二厚度。 第二厚度大于第一厚度。 第一晶体管具有由半导体层的第一部分形成的第一有源区。 第二晶体管具有由半导体层的第二部分形成的第二有源区。 第一晶体管可以是平面晶体管，例如，第二晶体管可以是多栅极晶体管。

    Methods and structures for planar and multiple-gate transistors formed on SOI
    100.
    发明授权
    Methods and structures for planar and multiple-gate transistors formed on SOI 有权
    在SOI上形成的平面和多栅极晶体管的方法和结构

    公开(公告)号：US07180134B2

    公开(公告)日：2007-02-20

    申请号：US10823158

    申请日：2004-04-13

    申请人： Fu-Liang Yang ,  Yee-Chia Yeo ,  Chenming Hu

    发明人： Fu-Liang Yang ,  Yee-Chia Yeo ,  Chenming Hu

    IPC分类号： H01L27/01 ,  H01L27/12

    CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7854

    摘要： A semiconductor device includes an insulator layer, a semiconductor layer, a first transistor, and a second transistor. The semiconductor layer is overlying the insulator layer. A first portion of the semiconductor layer has a first thickness. A second portion of the semiconductor layer has a second thickness. The second thickness is larger than the first thickness. The first transistor has a first active region formed from the first portion of the semiconductor layer. The second transistor has a second active region formed from the second portion of the semiconductor layer. The first transistor may be a planar transistor and the second transistor may be a multiple-gate transistor, for example.

    摘要翻译： 半导体器件包括绝缘体层，半导体层，第一晶体管和第二晶体管。 半导体层覆盖绝缘体层。 半导体层的第一部分具有第一厚度。 半导体层的第二部分具有第二厚度。 第二厚度大于第一厚度。 第一晶体管具有由半导体层的第一部分形成的第一有源区。 第二晶体管具有由半导体层的第二部分形成的第二有源区。 第一晶体管可以是平面晶体管，例如，第二晶体管可以是多栅极晶体管。