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    Doping of semiconductor fin devices
    1.
    发明授权
    Doping of semiconductor fin devices 有权
    掺杂半导体鳍片器件

    公开(公告)号：US08790970B2

    公开(公告)日：2014-07-29

    申请号：US11446697

    申请日：2006-06-05

    申请人： Yee-Chia Yeo ,  Ping-Wei Wang ,  Hao-Yu Chen ,  Fu-Liang Yang ,  Chenming Hu

    发明人： Yee-Chia Yeo ,  Ping-Wei Wang ,  Hao-Yu Chen ,  Fu-Liang Yang ,  Chenming Hu

    IPC分类号： H01L21/84

    CPC分类号： H01L29/785 ,  H01L21/26586 ,  H01L29/66803

    摘要： A semiconductor structure includes of a plurality of semiconductor fins overlying an insulator layer, a gate dielectric overlying a portion of said semiconductor fin, and a gate electrode overlying the gate dielectric. Each of the semiconductor fins has a top surface, a first sidewall surface, and a second sidewall surface. Dopant ions are implanted at a first angle (e.g., greater than about 7°) with respect to the normal of the top surface of the semiconductor fin to dope the first sidewall surface and the top surface. Further dopant ions are implanted with respect to the normal of the top surface of the semiconductor fin to dope the second sidewall surface and the top surface.

    摘要翻译： 半导体结构包括覆盖绝缘体层的多个半导体鳍片，覆盖所述半导体鳍片的一部分的栅极电介质和覆盖栅极电介质的栅电极。 每个半导体翅片具有顶表面，第一侧壁表面和第二侧壁表面。 掺杂离子相对于半导体鳍片的顶表面的法线以第一角度（例如，大于约7°）注入，以掺杂第一侧壁表面和顶表面。 相对于半导体鳍片的顶表面的法线注入另外的掺杂剂离子以掺杂第二侧壁表面和顶表面。

    Gate electrode for a semiconductor fin device
    4.
    发明申请
    Gate electrode for a semiconductor fin device 有权
    用于半导体鳍片器件的栅电极

    公开(公告)号：US20070111454A1

    公开(公告)日：2007-05-17

    申请号：US11649453

    申请日：2007-01-03

    申请人： Yee-Chia Yeo ,  Hao-Yu Chen ,  Fu-Liang Yang ,  Chenming Hu

    发明人： Yee-Chia Yeo ,  Hao-Yu Chen ,  Fu-Liang Yang ,  Chenming Hu

    IPC分类号： H01L21/336

    CPC分类号： H01L29/785 ,  H01L29/66795

    摘要： A method for forming a gate electrode for a multiple gate transistor provides a doped, planarized gate electrode material which may be patterned using conventional methods to produce a gate electrode that straddles the active area of the multiple gate transistor and has a constant transistor gate length. The method includes forming a layer of gate electrode material having a non-planar top surface, over a semiconductor fin. The method further includes planarizing and doping the gate electrode material, without doping the source/drain active areas, then patterning the gate electrode material. Planarization of the gate electrode material may take place prior to the introduction and activation of dopant impurities or it may follow the introduction arid activation of dopant impurities. After the gate electrode is patterned, dopant impurities are selectively introduced to the semiconductor fin to form source/drain regions.

    摘要翻译： 用于形成多栅极晶体管的栅电极的方法提供掺杂的平面化栅电极材料，其可以使用常规方法进行图案化以产生跨越多栅极晶体管的有源区并具有恒定晶体管栅极长度的栅电极。 该方法包括在半导体鳍上形成具有非平面顶表面的栅电极材料层。 该方法还包括对栅电极材料进行平面化和掺杂，而不掺杂源极/漏极有源区，然后对栅电极材料进行构图。 栅电极材料的平面化可以在引入和激活掺杂剂杂质之前进行，或者可以引入和掺杂杂质的激活。 在栅电极被图案化之后，掺杂剂杂质被选择性地引入半导体鳍片以形成源极/漏极区域。

    CMOS inverters configured using multiple-gate transistors
    5.
    发明授权
    CMOS inverters configured using multiple-gate transistors 有权
    使用多栅极晶体管配置的CMOS反相器

    公开(公告)号：US07214991B2

    公开(公告)日：2007-05-08

    申请号：US10313887

    申请日：2002-12-06

    申请人： Yee-Chia Yeo ,  Fu-Liang Yang ,  Chenming Hu

    发明人： Yee-Chia Yeo ,  Fu-Liang Yang ,  Chenming Hu

    IPC分类号： H01L29/76

    CPC分类号： H01L27/1211 ,  H01L21/823828 ,  H01L21/845 ,  H01L27/092 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7854

    摘要： An inverter that includes a first multiple-gate transistor including a source connected to a power supply, a drain connected to an output terminal, and a gate electrode; a second multiple-gate transistor including a source connected to a ground, a drain connected to the output terminal, and a gate electrode; and an input terminal connected to the gate electrodes of the first and second multiple-gate transistors. Each of the first and second multiple-gate transistors may further include a semiconductor fin formed vertically on an insulating layer on top of a substrate, a gate dielectric layer overlying the semiconductor fin, and a gate electrode wrapping around the semiconductor fin separating the source and drain regions.

    摘要翻译： 一种逆变器，包括：第一多栅极晶体管，其包括连接到电源的源极，连接到输出端子的漏极和栅极电极; 第二多栅极晶体管，其包括连接到地的源极，连接到输出端子的漏极和栅极电极; 以及连接到第一和第二多栅极晶体管的栅电极的输入端子。 第一和第二多栅极晶体管中的每一个还可以包括在衬底顶部的绝缘层上垂直形成的半导体鳍片，覆盖在半导体鳍片上的栅极电介质层，以及围绕分离源极的半导体鳍状物包围的栅电极，以及 漏区。

    Doping of semiconductor fin devices
    6.
    发明申请
    Doping of semiconductor fin devices 有权

    公开(公告)号：US20060220133A1

    公开(公告)日：2006-10-05

    申请号：US11446890

    申请日：2006-06-05

    申请人： Yee-Chia Yeo ,  Ping-Wei Wang ,  Hao-Yu Chen ,  Fu-Liang Yang ,  Chenming Hu

    发明人： Yee-Chia Yeo ,  Ping-Wei Wang ,  Hao-Yu Chen ,  Fu-Liang Yang ,  Chenming Hu

    IPC分类号： H01L27/12

    CPC分类号： H01L29/785 ,  H01L21/26586 ,  H01L29/66803

    摘要： A semiconductor structure includes of a plurality of semiconductor fins overlying an insulator layer, a gate dielectric overlying a portion of said semiconductor fin, and a gate electrode overlying the gate dielectric. Each of the semiconductor fins has a top surface, a first sidewall surface, and a second sidewall surface. Dopant ions are implanted at a first angle (e.g., greater than about 7°) with respect to the normal of the top surface of the semiconductor fin to dope the first sidewall surface and the top surface. Further dopant ions are implanted with respect to the normal of the top surface of the semiconductor fin to dope the second sidewall surface and the top surface.

    Semiconductor device with high-k gate dielectric
    10.
    发明申请
    Semiconductor device with high-k gate dielectric 有权
    具有高k栅极电介质的半导体器件

    公开(公告)号：US20050035345A1

    公开(公告)日：2005-02-17

    申请号：US10832020

    申请日：2004-04-26

    申请人： Chun-Chieh Lin ,  Wen-Chin Lee ,  Chenming Hu ,  Shang-Chih Chen ,  Chih-Hao Wang ,  Fu-Liang Yang ,  Yee-Chia Yeo

    发明人： Chun-Chieh Lin ,  Wen-Chin Lee ,  Chenming Hu ,  Shang-Chih Chen ,  Chih-Hao Wang ,  Fu-Liang Yang ,  Yee-Chia Yeo

    IPC分类号： H01L21/28 ,  H01L21/8234 ,  H01L29/51 ,  H01L29/06

    CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/823462 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

    摘要： An integrated circuit includes a substrate, a first transistor, and a second transistor. The first transistor has a first gate dielectric portion located between a first gate electrode and the substrate. The first gate dielectric portion includes a first high-permittivity dielectric material and/or a second high-permittivity dielectric material. The first gate dielectric portion has a first equivalent silicon oxide thickness. The second transistor has a second gate dielectric portion located between a second gate electrode and the substrate. The second gate dielectric portion includes the first high-permittivity dielectric material and/or the second high-permittivity dielectric material. The second gate dielectric portion has a second equivalent silicon oxide thickness. The second equivalent silicon oxide thickness may be different than the first equivalent silicon oxide thickness.

    摘要翻译： 集成电路包括衬底，第一晶体管和第二晶体管。 第一晶体管具有位于第一栅电极和衬底之间的第一栅电介质部分。 第一栅介质部分包括第一高介电常数电介质材料和/或第二高介电常数介电材料。 第一栅介质部分具有第一等效氧化硅厚度。 第二晶体管具有位于第二栅电极和衬底之间的第二栅介质部分。 第二栅介质部分包括第一高介电常数电介质材料和/或第二高介电常数介电材料。 第二栅介质部分具有第二等效氧化硅厚度。 第二等效氧化硅厚度可以不同于第一等效氧化硅厚度。