公开(公告)号：US5576656A

公开(公告)日：1996-11-19

申请号：US414103

申请日：1995-03-31

Applicant: David C. McClure

Inventor： David C. McClure

IPC: G05F3/24 ,  G05F1/46 ,  G05F1/56 ,  H03F3/34 ,  H03F3/343 ,  H03F3/347 ,  H03F3/45 ,  G05F1/10

CPC classification number: H03F3/45479 ,  G05F1/465 ,  H03F3/45766 ,  H03F2203/45454 ,  H03F2203/45466 ,  H03F2203/45504 ,  H03F2203/45508

Abstract: An output driver circuit for an integrated circuit is disclosed, where the output driver drives an output terminal with a high logic level having a voltage limited from the power supply voltage of the integrated circuit. The limited voltage is provided by applying a limited output high voltage to an output buffer, such that the drive signal applied to the gate of the pull-up transistor in the output driver is limited by the limited output high voltage applied to the output buffer. A voltage reference and regulator circuit for generating the limited output high voltage, or for generating a reference voltage for application to a circuit other than an output buffer and that demands sink current, is also disclosed. The voltage reference and regulator is based on a current mirror, in which the sum of the current in the current mirror is controlled by a bias current source which may be dynamically controlled within the operating cycle or programmed by way of fuses. A sink current path circuit, according to various alternatives, is disclosed as providing an additional sink current path in the event that the limited output high voltage, or reference voltage, exceeds the desired level.

Abstract translation: 公开了一种用于集成电路的输出驱动器电路，其中输出驱动器驱动具有从集成电路的电源电压限制的电压的高逻辑电平的输出端子。 通过将有限的输出高电压施加到输出缓冲器来提供有限的电压，使得施加到输出驱动器中的上拉晶体管的栅极的驱动信号受到施加到输出缓冲器的受限输出高电压的限制。 还公开了一种用于产生有限输出高电压或用于产生用于施加到除输出缓冲器之外的电路并且需要吸收电流的参考电压的电压基准和调节器电路。 电压参考和调节器基于电流镜，其中电流镜中的电流之和由偏置电流源控制，偏置电流源可以在操作周期内动态控制或通过熔丝进行编程。 根据各种替代方案，汇流电流路径电路被公开为在有限输出高电压或参考电压超过期望水平的情况下提供额外的灌电流通路。

公开(公告)号：US5574688A

公开(公告)日：1996-11-12

申请号：US438903

申请日：1995-05-10

Applicant: David C. McClure ,  Thomas Teel

Inventor： David C. McClure ,  Thomas Teel

IPC: G11C29/00 ,  G11C13/00

CPC classification number: G11C29/80 ,  G11C29/84

Abstract: A memory device, which communicates with external address and data buses, includes a circuit for mapping a redundant memory column having a redundant memory cell to an address of a defective memory column. An enable line communicates with the redundant memory column and selectively carries active and inactive signal levels for respectively enabling and disabling communication between the data bus and the redundant memory cell. An address decoder receives an address signal on the address bus and generates the active level on the enable line when the value of the address signal equals the address of the defective memory cell. A driver precharges the enable line to the inactive level while the address signal is invalid.

Abstract translation: 与外部地址和数据总线通信的存储器件包括用于将具有冗余存储器单元的冗余存储器列映射到有缺陷的存储器列的地址的电路。 使能线与冗余存储器列通信，并选择性地承载有源和非活动信号电平，以分别启用和禁用数据总线与冗余存储单元之间的通信。 地址解码器在地址总线上接收地址信号，并且当地址信号的值等于有缺陷的存储单元的地址时，在使能线上产生有效电平。 当地址信号无效时，驱动器将使能线路预充电到无效电平。

公开(公告)号：US5572456A

公开(公告)日：1996-11-05

申请号：US114747

申请日：1993-08-31

Applicant: David C. McClure

Inventor： David C. McClure

IPC: G06F12/08 ,  H03K19/08 ,  G11C15/04

CPC classification number: G06F12/0895 ,  H03K19/08

Abstract: A system for providing a CMOS NOR function that is distributed across a number of devices located on different chips. Specifically the present invention may be implemented in tag RAMs to provide expanded addressing. In other words, larger addresses may be processed using the present invention. This function is provided by using some transistors on each chip as part of the CMOS NOR gate. The tag RAM includes: a first input for receiving a first portion of an address, a second input for receiving a second portion of the address; a memory array connected to the first input; a comparator connected to the memory array and the second input, wherein the comparator has an output that produces an output signal in response to receiving a first signal from the second input and a second signal from the memory array; a first transistor having a gate connected to the output of the comparator, a first source/drain connected to a first pin, and a second source/drain connected to a second pin; and a second transistor having a gate connected to the output of the comparator, a first source/drain connected to the output pin, a second source/drain connected to a lower power supply voltage source.

Abstract translation: 一种用于提供分布在位于不同芯片上的多个设备的CMOS NOR功能的系统。 具体地，本发明可以在标签RAM中实现以提供扩展寻址。 换句话说，可以使用本发明来处理较大的地址。 该功能通过在每个芯片上使用一些晶体管作为CMOS或非门的一部分来提供。 标签RAM包括：用于接收地址的第一部分的第一输入端，用于接收地址的第二部分的第二输入; 连接到第一输入的存储器阵列; 连接到存储器阵列和第二输入的比较器，其中所述比较器具有响应于从所述第二输入接收第一信号和来自所述存储器阵列的第二信号而产生输出信号的输出; 第一晶体管，其具有连接到比较器的输出的栅极，连接到第一引脚的第一源极/漏极和连接到第二引脚的第二源极/漏极; 以及第二晶体管，具有连接到所述比较器的输出的栅极，连接到所述输出引脚的第一源极/漏极，连接到较低电源电压源的第二源极/漏极。

公开(公告)号：US5544097A

公开(公告)日：1996-08-06

申请号：US414918

申请日：1995-03-31

Applicant: David C. McClure ,  Mehdi Zamanian

Inventor： David C. McClure ,  Mehdi Zamanian

IPC: G11C11/413 ,  G11C5/14 ,  G11C11/412 ,  G11C11/40

CPC classification number: G11C5/147 ,  G11C11/412

Abstract: A memory cell having a first device operable to selectively conduct and coupled between a first cell node and a low voltage reference node and a second device operable to selectively conduct and coupled between a second cell node and the low voltage reference node. The memory cell further includes a first and second data line and circuitry for receiving a system level voltage and for biasing the first and second data lines at a first and second data voltage, respectively. Still further, the memory cell includes circuitry for coupling the first and second data line to the first and second cell node, respectively, such that a logical high voltage is selectively written to one of the first and second cell nodes while a logical low is written to the other of the first and second cell nodes during a write operation. Still further, the memory cell includes a voltage source node for receiving a cell voltage and circuitry for coupling the voltage source node to the first and second cell nodes. Lastly, the memory cell includes cell voltage circuitry for generating the cell voltage, wherein the cell voltage circuitry is operable to output a cell voltage less than the system level voltage.

Abstract translation: 一种具有第一装置的存储器单元，其可操作以选择性地传导和耦合在第一单元节点和低电压参考节点之间，以及可操作以选择性地传导和耦合在第二单元节点与低电压参考节点之间的第二设备。 存储单元还包括第一和第二数据线以及用于接收系统电平电压并用于分别以第一和第二数据电压偏置第一和第二数据线的电路。 另外，存储单元包括用于将第一和第二数据线分别耦合到第一和第二单元节点的电路，使得逻辑高电压有选择地写入第一和第二单元节点中的一个，同时写入逻辑低电平 在写入操作期间到第一和第二小区节点中的另一个。 此外，存储单元包括用于接收单元电压的电压源节点和用于将电压源节点耦合到第一和第二单元节点的电路。 最后，存储单元包括用于产生单元电压的单元电压电路，其中单元电压电路可操作以输出小于系统电平电压的单元电压。

公开(公告)号：US5513335A

公开(公告)日：1996-04-30

申请号：US970188

申请日：1992-11-02

Applicant: David C. McClure

Inventor： David C. McClure

IPC: G06F12/08 ,  G06F12/00 ,  G06F15/00 ,  G11C13/00

CPC classification number: G06F12/0831 ,  G06F12/0853

Abstract: A cache tag memory device having a memory array comprising a first single-port memory array, a second single-port memory array, and a dual-port memory array. A first port, accessed by a local processor, may read from and write to its corresponding single-port memory array and the dual-port memory array. A second port, accessed through a global system bus, may also read from and write to its corresponding second single-port memory array and the dual-port memory array. Both ports operate asynchronously relative to each other. Status bits indicating the status of the entries in the first and second single-port memory arrays are stored in the dual-port memory array and may be altered by the global system while the local processor is performing its operations.

Abstract translation: 具有包括第一单端口存储器阵列，第二单端口存储器阵列和双端口存储器阵列的存储器阵列的高速缓存标签存储器设备。 由本地处理器访问的第一个端口可以从其对应的单端口存储器阵列和双端口存储器阵列读取和写入。 通过全局系统总线访问的第二个端口也可以从其对应的第二单端口存储器阵列和双端口存储器阵列读取和写入。 两个端口相对于彼此异步运行。 指示第一和第二单端口存储器阵列中的条目的状态的状态位存储在双端口存储器阵列中，并且可以在本地处理器执行其操作时被全局系统改变。

公开(公告)号：US5485430A

公开(公告)日：1996-01-16

申请号：US306527

申请日：1994-09-15

Applicant: David C. McClure

Inventor： David C. McClure

IPC: G11C7/06 ,  G11C8/00 ,  G11C7/00

CPC classification number: G11C7/065

Abstract: A method and circuit is provided for reading a memory array which utilizes multiple clocking signals during one read cycle to enable a dynamic sense amplifier to read data from the memory array. A dynamic sense amplifier is connected to an input line, a complementary input line, and a latch. A first equilibrating signal is input into the sense amplifier, followed thereafter by a first clocking signal. The first clocking signal enables the sense amplifier to read data on the input line and complementary input line. While the sense amplifier reads the data, the sense amplifier is isolated from the input and complementary input lines. Based upon the data read by the sense amplifier, an output state is provided for the latch. After reading the data, the sense amplifier is reconnected to the input and complementary input lines. A second clocking signal then enables the sense amplifier to read the data on the input and complementary input lines a second time, and the sense amplifier is isolated from the input and complementary input lines. The output state of the latch may or may not change based upon the data read by the sense amplifier the second time.

Abstract translation: 提供了一种方法和电路，用于读取在一个读取周期期间利用多个时钟信号的存储器阵列，以使得动态读出放大器能够从存储器阵列读取数据。 动态读出放大器连接到输入线，互补输入线和锁存器。 第一平衡信号被输入到读出放大器中，之后是第一时钟信号。 第一个时钟信号使读出放大器能够读取输入线和互补输入线上的数据。 当读出放大器读取数据时，读出放大器与输入和输入线互为隔离。 基于由读出放大器读取的数据，为锁存器提供输出状态。 在读取数据之后，读出放大器被重新连接到输入和补充输入线。 第二时钟信号然后使得读出放大器能够在第二次读取输入和互补输入线上的数据，并且读出放大器与输入和互补输入线隔离。 基于第二次由读出放大器读取的数据，锁存器的输出状态可以也可以不改变。

公开(公告)号：US5483489A

公开(公告)日：1996-01-09

申请号：US307332

申请日：1994-09-16

Applicant: David C. McClure

Inventor： David C. McClure

IPC: G11C7/06 ,  G11C7/00

CPC classification number: G11C7/065 ,  G11C7/062

Abstract: A memory system comprising a memory array having at least two pairs of data lines, first and second data lines corresponding to columns in the memory array. The memory array also includes two level shifter circuits, a first shifter circuit connected to the first lines and a second level shifter circuit connected to the second data lines, wherein the level shifter circuits produce output signals and may be enabled and disabled. A selection signal is used to selectively enable and disable the level shifter circuits, wherein one pair of data lines may be selected. An amplification circuit is connected to the level shifters for amplifying the output signals from the level shifter circuits, and a logic circuit is used to generate logic output signals in response to the amplified output signals from the amplification circuit.

Abstract translation: 一种存储器系统，包括具有至少两对数据线的存储器阵列，对应于存储器阵列中的列的第一和第二数据线。 存储器阵列还包括两个电平移位器电路，连接到第一线的第一移位器电路和连接到第二数据线的第二电平移位器电路，其中电平移位器电路产生输出信号并且可以被使能和禁止。 选择信号用于选择性地启用和禁用电平移位器电路，其中可以选择一对数据线。 放大电路连接到电平移位器，用于放大来自电平移位器电路的输出信号，并且逻辑电路用于响应于来自放大电路的放大的输出信号产生逻辑输出信号。

公开(公告)号：US5471415A

公开(公告)日：1995-11-28

申请号：US085588

申请日：1993-06-30

Applicant: David C. McClure

Inventor： David C. McClure

IPC: G06F12/08 ,  G11C7/10 ,  G11C11/41 ,  G11C11/413 ,  G11C11/417 ,  G11C15/04 ,  G11C15/00 ,  G11C13/00

CPC classification number: G06F12/0895 ,  G11C7/1006

Abstract: A comparator system for a cache tag RAM memory that makes use of data bus lines already available on the cache tag RAM. The true data bus lines are connected together at a connection point and form a "wired" connection or configuration. A "wired" connection may be for example, a "wired OR" "wired NOR" "wired AND" or "wired NAND" according to the present invention. The complement data bus lines on the cache tag RAM are connected in a similar fashion. The comparator system is connected to the cache tag RAM data bus lines and generates a hit or miss signal based on the data on the cache tag RAM data bus lines and input data that controls transistors connected to the cache tag RAM data bus lines, resulting in a faster comparison function.

Abstract translation: 用于缓存标签RAM存储器的比较器系统，其利用缓存标签RAM上已经可用的数据总线。 真正的数据总线在连接点连接在一起并形成“有线”连接或配置。 “有线”连接可以是例如根据本发明的“有线或”有线NOR“有线AND”或“有线NAND”。 缓存标签RAM上的补码数据总线以类似的方式连接。 比较器系统连接到高速缓存标签RAM数据总线，并基于高速缓存标签RAM数据总线上的数据和控制连接到高速缓存标签RAM数据总线的晶体管的输入数据产生命中或未命中信号，导致 更快的比较功能。

公开(公告)号：US5455802A

公开(公告)日：1995-10-03

申请号：US995581

申请日：1992-12-22

Applicant: David C. McClure

Inventor： David C. McClure

IPC: G11C11/419 ,  G11C7/06 ,  G11C11/409 ,  G11C11/34

CPC classification number: G11C7/065

Abstract: A method and circuit for reading a memory array by utilizing dual dynamic sense amplifiers. A first and a second dynamic sense amplifier are connected to an input line and complementary input line. A latch and a clocking circuit are also connected to the two dynamic sense amplifiers. Initially, an equilibrating signal is input into both sense amplifiers. A first clocking signal and a first isolating signal are then input into the first dynamic sense amplifier. The first clocking signal enables the first sense amplifier to read the data on the input and complementary input lines, while the first isolating signal isolates the first sense amplifier from the input and complementary input lines. An output is then provided to the latch based upon the data read by the first sense amplifier. A second clocking signal and a second isolating signal are then input into the second sense amplifier to enable the second sense amplifier to read the data on the input and complementary input lines. The state of the latch may or may not change based upon the data read by the second sense amplifier.

Abstract translation: 一种利用双动态读出放大器读取存储器阵列的方法和电路。 第一和第二动态读出放大器连接到输入线和互补输入线。 锁存器和时钟电路也连接到两个动态读出放大器。 最初，平衡信号被输入到两个读出放大器中。 然后将第一时钟信号和第一隔离信号输入到第一动态读出放大器。 第一时钟信号使得第一读出放大器能够读取输入和互补输入线上的数据，而第一隔离信号将第一读出放大器与输入和互补输入线隔离。 然后基于由第一读出放大器读取的数据将输出提供给锁存器。 然后将第二时钟信号和第二隔离信号输入到第二读出放大器，以使得第二读出放大器能够读取输入和互补输入线上的数据。 基于由第二读出放大器读取的数据，锁存器的状态可以或可以不改变。

公开(公告)号：US5455798A

公开(公告)日：1995-10-03

申请号：US199859

申请日：1994-02-22

Applicant: David C. McClure

Inventor： David C. McClure

IPC: G11C11/413 ,  G11C29/00 ,  G11C29/04 ,  G11C7/00

CPC classification number: G11C29/83 ,  G11C29/846 ,  G11C29/781

Abstract: An integrated circuit memory is disclosed which has its primary memory array arranged into blocks and which has redundant columns, each of which can replace a column in any one of the blocks. The redundant columns are selected by way of a redundant column decoder associated with each column, each of which includes a set of address fuses into which an address is programmed, responsive to which its associated redundant column is to be selected. A plurality of redundant sense amplifiers are each associated with selected redundant columns, and are each controlled to begin the sense operation prior to propagation of the address signal through the redundant column decoders and summing circuitry. In the event that the received memory address does not match any of the programmed values in the redundant column decoders associated with a redundant sense amplifier, the sense operation is terminated. In this way, the sense operation is not delayed by the additional delay required for redundant decoding and propagation of the redundant address signals, and thus the access time penalty for accessing a redundant memory cell is much reduced or eliminated. The coupling of each redundant sense amplifier is controlled by a redundant multiplexer associated with each of the input/output terminals. Each redundant multiplexer receives the redundant column select signals from each associated redundant column decoder, and includes fuses which indicate if its input/output terminal is to be placed in communication with its associated sense amplifier upon selection of a redundant column.

Abstract translation: 公开了一种集成电路存储器，其具有排列成块的主存储器阵列，并且具有冗余列，每个列可替代任何一个块中的列。 冗余列通过与每个列相关联的冗余列解码器来选择，每个列包括一组地址熔丝，地址被编程到其中，响应于哪个相关联的冗余列被选择。 多个冗余读出放大器各自与所选择的冗余列相关联，并且每个冗余读出放大器都被控制以在通过冗余列解码器和求和电路传播地址信号之前开始感测操作。 在接收到的存储器地址与冗余读出放大器相关联的冗余列解码器中的任何编程值不匹配的情况下，感测操作终止。 以这种方式，由于冗余解码和冗余地址信号的传播所需的附加延迟，感测操作不会延迟，因此大大减少或消除了用于访问冗余存储器单元的访问时间损失。 每个冗余读出放大器的耦合由与每个输入/输出端子相关联的冗余多路复用器控制。 每个冗余多路复用器接收来自每个相关联的冗余列解码器的冗余列选择信号，并且包括指示其选择冗余列时是否将其输入/输出端子与其相关联的读出放大器通信的熔丝。